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nxp semiconductors data sheet: technical data document number: imx8mdqlqcec rev. 0.1, 05/2018 ordering information see table 2 on page 6 ? 2018 nxp b.v. MIMX8MQ7DVAJZAA mimx8mq6dvajzaa mimx8md7dvajzaa mimx8md6dvajzaa mimx8mq5dvajzaa package information plastic package fbga 17 x 17 mm, 0.65 mm pitch 1 i.mx 8m dual / 8m quadlite / 8m quad introduction the i.mx 8m dual / 8m quadlite / 8m quad processors represent nxps latest market of connected streaming audio/video devices, scanning/imaging devices, and various devices requiring hi gh-performance, low-power processors. the i.mx 8m dual / 8m quadlite / 8m quad processors feature advanced impleme ntation of a quad arm ? cortex ? -a53 core, which operates at speeds of up to 1.5 ghz. a general purpose cortex ? -m4 core processor is for low-power processing. the dram controller supports 32-bit/16-bit lp ddr4, ddr4, and ddr3l memory. there are a number of other interfaces for connecting peripherals, such as wlan, bluetooth, gps, displays, and camera sensors. the i.mx 8m quad and i.mx 8m dual processors have hardware acceleration for video playback up to 4k, and can drive the video outputs up to 60 fps. although the i.mx 8m quadlite processor does not have hardwa re acceleration for video decode, it allows for video playback with software decoders if needed. i.mx 8m dual / 8m quadlite / 8m quad applications processors data sheet for consumer products 1. i.mx 8m dual / 8m quadlite / 8m quad introduction . . . . . . 1 1.1. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.2. ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2. modules list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.1. recommended connections for unused interfaces . . . . 12 3. electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.1. chip-level conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.2. power supplies requirements and restrictions . . . . . . . 24 3.3. pll electrical characteristics . . . . . . . . . . . . . . . . . . . . 26 3.4. on-chip oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.5. i/o dc parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 3.6. i/o ac parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 3.7. output buffer impedance parameters . . . . . . . . . . . . . . 34 3.8. system modules timing . . . . . . . . . . . . . . . . . . . . . . . . 36 3.9. external peripheral interface parameters . . . . . . . . . . . 37 4. boot mode configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 4.1. boot mode configuration pins . . . . . . . . . . . . . . . . . . . 71 4.2. boot device interface allocation . . . . . . . . . . . . . . . . . . 72 5. package information and contact assignments . . . . . . . . . . . . 73 5.1. 17 x 17 mm package information . . . . . . . . . . . . . . . . . 73 5.2. ddr pin function list for 17 x 17 mm package . . . . . . 9 2 6. revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
i.mx 8m dual / 8m quadlite / 8m quad applications processors da ta sheet for consumer pr oducts, rev. 0.1, 05/2018 2 nxp semiconductors i.mx 8m dual / 8m quadlite / 8m quad introduction table 1. features subsystem feature arm cortex-a53 mpcore platform qua d symmetric cortex-a53 process ors: ? 32 kb l1 instruction cache ? 32 kb l1 data cache ? support l1 cache rams pr otection with parity/ecc support of 64-bit armv8-a architecture: ? 1 mb unified l2 cache ? support l2 cache ra ms protection with ecc ? frequency of 1.5 ghz arm cortex-m4 core platform 1 6 kb l1 instruction cache 16 kb l1 data cache 256 kb tightly coupled memory (tcm) connectivity two pci e xpress gen2 interfaces two usb 3.0/2.0 cont rollers with integrated phy interfaces two ultra secure digital host controller (usdhc) interfaces one gigabit ethernet controller with support for eee, ethernet avb, and ieee 1588 four universal asynchronous recei ver/transmitter (uart) modules four i 2 c modules three spi modules external memory interface 32/16- bit dram inte rface: lpddr4-3200, ddr4-2400, ddr3l-1600 8-bit nand-flash emmc 5.0 flash spi nor flash quadspi flash with support for xip gpio and pin multiplexing gpio m odules with inte rrupt capability input/output multiplexing controll er (iomuxc) to provide centra lized pad control on-chip memory boot rom (128 kb) on-chip ram (128 kb + 32 kb) power management temperature sens or with programmable trip point s flexible power domain partitioning with int ernal power switches to support efficient power management
i.mx 8m dual / 8m quadlite / 8m quad introduction i.mx 8m dual / 8m quadlite / 8m quad applications processors da ta sheet for consumer pr oducts, rev. 0.1, 05/2018 nxp semiconductors 3 multimedia video processing unit: ? 4kp60 hevc/h.265 main, and main 10 decoder ? 4kp60 vp9 decoder ? 4kp30 avc/h.264 decoder ? 1080p60 mpeg-2, mpeg-4p2, vc-1, vp8, rv9, avs, mjpeg, h.263 d ecoder graphic processing unit: ? 4 shader ? 267 million triangles/sec ? 1.6 giga pixel/sec ? 32 gflops 32-bit or 64 gflops 16-bit ? support opengl es 1.1, 2.0, 3. 0, 3.1, open cl 1.2, and vulkan hdmi display interface: ? hdmi 2.0a supporting one display: resolution up to 4096 x 216 0 at 60 hz, support hdcp 2.2 and hdcp 1.4 1 ? 20+ audio interface s 32-bit @ 384 khz fs, with time division multiplexing (tdm) support ? s/pdif input and output ? audio return channel (arc) on hdmi ? upscale hd graphics to 4k for display ? downscale 4k video to hd for display ? display port ? embedded display port mipi-dsi display interface: ? mipi-dsi 4 channels supporting one display, resolution up to 1920 x 1080 at 60 hz ? lcdif display controller ? output can be lcdi f output or dc display controller output audio: ? s/pdif input and output ? five synchronous audio interfa ce (sai) modules supporting i2s , ac97, tdm, and codec/dsp interfaces, including one sai with 16 tx and 16 rx ch annels, one sai with 8 tx and 8 rx channels, a nd three sai with 2 t x and 2 rx channels ? one sai for 8 tx channe ls for hdmi output audio ? one s/pdif input for hdmi arc input camera inputs: ? two mipi-csi2 camera inputs (4-lane each) security resource dom ain controller (rdc) supports four domains and up to eight regions arm trustzone (tz) architecture on-chip ram (ocram) secure regi on protection using ocram contro ller high assurance boot (hab) cryptographic accele ration and assura nce (caam) module secure non-volatile st orage (snvs): secure real-time clock (rtc ) secure jtag controller (sjc) table 1. features (continued) subsystem feature
i.mx 8m dual / 8m quadlite / 8m quad applications processors da ta sheet for consumer pr oducts, rev. 0.1, 05/2018 4 nxp semiconductors i.mx 8m dual / 8m quadlite / 8m quad introduction note the actual feature set depends on the part numbers as described in table 2 . functions such as display and camera interfaces, and connectivi ty interfaces, may not be enable d for specific part numbers. system debug arm coresight d ebug and trace architecture tpiu to support off-chi p real-time trace etf with 4 kb internal stora ge to provide trace buffering unified trace capabilit y for quad cortex-a53 and cortex-m4 cpus cross triggering interface (cti) support for 5-pin (jtag) debug interface 1 please contact the nxp sales and marketing team for order detai ls on hdcp enable parts. table 1. features (continued) subsystem feature
i.mx 8m dual / 8m quadlite / 8m quad introduction i.mx 8m dual / 8m quadlite / 8m quad applications processors da ta sheet for consumer pr oducts, rev. 0.1, 05/2018 nxp semiconductors 5 1.1 block diagram figure 1 shows the functional modules in the i.mx 8m dual / 8m quadlite / 8m quad processor system. figure 1. i.mx 8m dual / 8m quadl ite / 8m quad sy stem block diag ram ^???u}v??}o ^u??d?? du????^v?}? d]u??? ^?:d' t?z}p?? >}w}?u^?]??wh }vv?]]??v/lk '?z?v? ~/???uuvs wtd?e do?]u] h^?xl?xkd'?? ^lw/&z?vd?u d/w/^/]??o?? ,d/?x}??? ???vodu}?? ^?]?? d???}v zd]?z?? ^?o}l &?<?^?}?p zv}ueu? ??<^?zd d]vwhwo?(}?u y}???r?? ??</rz ??<rz eke &wh d>?z }???rde </rz <rz ??<dd ?'??z]?we^z? k?v'>l^?xu>x?usolv ewzer?? ??dd?l^? eed>~,? y^w/~y/w du?d}v]?}? /?^l^/? w/?x??~rovuz hzd?eu?d?? /??eu^w/?? ,w?x? d/w/^/?????? er
i.mx 8m dual / 8m quadlite / 8m quad applications processors da ta sheet for consumer pr oducts, rev. 0.1, 05/2018 6 nxp semiconductors i.mx 8m dual / 8m quadlite / 8m quad introduction 1.2 ordering information table 2 shows examples of orderable sa mple part numbers covered by thi s data sheet. this table does not include all possible orderabl e part numbers. if your desired pa rt number is not listed in the table, or you have questions about available pa rts, contact your nxp represen tative. figure 2 describes the part number nomen clature so that the users can i dentify the characteristics of the specific part number. contact an nxp representa tive for additional details. table 2. orderable part numbers part number 1 1 part number require s a dolby vision tm license from dolby. options cortex-a53 cpu speed grade qualification tier temperature t j ( c) package MIMX8MQ7DVAJZAA 8m quad 1.5 ghz consumer 0 to +95 17 x 17 mm, 0.65 mm pitch, fbga mimx8mq6dvajzaa 8m quad 1.5 ghz consumer 0 to +95 17 x 17 mm, 0.65 mm pitch, fbga mimx8md7dvajzaa 8m dual 1.5 ghz consumer 0 to +95 17 x 17 mm, 0.65 mm pitch, fbga mimx8md6dvajzaa 8m dual 1.5 ghz consumer 0 to +95 17 x 17 mm, 0.65 mm pitch, fbga mimx8mq5dvajzaa 8m quad lite 1.5 ghz consumer 0 to +95 17 x 17 mm, 0.65 mm pitch, fbga
i.mx 8m dual / 8m quadlite / 8m quad introduction i.mx 8m dual / 8m quadlite / 8m quad applications processors da ta sheet for consumer pr oducts, rev. 0.1, 05/2018 nxp semiconductors 7 figure 2. part number nomenclatur ei.mx 8m dual / 8m quadlite / 8m quad processors *please contact the nxp sales and marketing team for order deta ils on hdcp enable parts. temperature (tj) + commercial: 0 to + 95 c d industrial: -40 to +105 c c frequency $$ 1.5 ghz jz 1.3 ghz hz package type rohs 17 x 17 mm, 0.65 mm pitch, fcbga bare die va qualification level m samples p mass production m special s i.mx 8 family part # series description i.mx 8mq quad core i.mx 8md dual core silicon rev a rev 1.0 a fusing % -a hdcp customer programmable * d hdcp nxp programmed c m imx8mq @ + vn $$ % a part differentiator @ vpu decode + dolby vision + hdr10 + gpu 7 vpu decode + hdr10 + gpu 6 gpu, no vpu 5
i.mx 8m dual / 8m quadlite / 8m quad applications processors da ta sheet for consumer pr oducts, rev. 0.1, 05/2018 8 nxp semiconductors modules list 2 modules list the i.mx 8m dual / 8m quadlite / 8m quad of processors contain a variety of digital and analog modules. table 3 describes these modules in alphabetical order. table 3. i.mx 8m dual / 8m qua dlite / 8m quad modules list block mnemonic block na me brief description apbh-dma nand flash and bch ecc dma controller dma controller used f or gpmi2 operation. arm arm platform the arm core plat form includes a quad cortex-a53 core and a cortex-m4 core. the cortex-a53 core includes associated sub-blocks, such as the level 2 cache controller, snoop c ontrol unit (scu), general int errupt controller (gic), private time rs, watchdog, and coresight debug modules. the cortex-m4 core is used as a customer microcontroller. bch binary-bch ecc processor the bch module provides up to 62-bit ecc encryption/decryption for nand flash controller (gpmi) caam cryptographic accelerator and assurance module caam is a cryptographic accelerator and assurance module. caam implements several encryption a nd hashing functions, a run-time integrity checker, entropy source generat or, and a pseudo random number generator (prng). the prng is cer tifiable by the cryptographic algorithm validation program (cav p) of the national institute o f standards and technology (nist). caam also implements a secure me mory mechanism. in i.mx 8m dual / 8m quadlite / 8m quad processors, the secure memory provided is 32 kb. ccm gpc src clock control module, general power controller, system reset controller these modules are responsible for clock and reset distribution in the system, and also for the system power management. csu central security unit the central security unit (csu) is resp onsible for setti ng comprehensive security policy within the i.mx 8m dual / 8m qua dlite / 8m quad platform. cti-0 cti-1 cti-2 cti-3 cti-4 cross trigger interface cross trig ger interface (cti) allows cro ss-triggering based on inputs from masters attached to ctis. the cti module is internal to the cor tex-a53 core platform. dap debug access port the dap provides real-time access for the d ebugger without halting the core to access: ? system memory and peripheral registers ? all debug configuration registers the dap also provides debugger access to jtag scan chains. dc display controller dua l display controller ddrc double data rate controller th e ddr controller has the follo wing features: ? supports 32/16-bit lpddr4- 3200, ddr4-2400, and ddr3l-1600 ? supports up to 8 gbyt e ddr memory space ecspi1 ecspi2 ecspi3 configurable spi full-duplex enha nced synchronous serial interfa ce, with data rate up to 52 mbit/s. configurable to support master/slave modes, four chip s elects to support multiple peripherals.
modules list i.mx 8m dual / 8m quadlite / 8m quad applications processors da ta sheet for consumer pr oducts, rev. 0.1, 05/2018 nxp semiconductors 9 eim nor-flash / psram i nterface the eim nor-flash / psram provide s: ? support for 16-bit (in muxed i/ o mode only) psr am memories (s ync and async operating mode s), at slo w frequency ? support for 16-bit (in muxed a nd non muxed i/o modes) nor-fla sh memories, at slow frequency ? multiple chip selects enet1 ethernet controller the ethernet media access controller (m ac) is designed to support 10/100/1000 mbps ethernet/ieee 802. 3 networks. an external tran sceiver interface and transceiver functi on are required to complete the interface to the media. the module has dedicated hardwa re to support the iee e 1588 standard. see the enet chapter of the i.mx 8m dual / 8m quadlite / 8m quad applications proc essor reference manual (imx8mdqlqrm) for details. gic generic interrupt controller the gic handles all interrupts f rom the various subsystems and is ready for virtualization. gpio1 gpio2 gpio3 gpio4 gpio5 general purpose i/o modules used for general purpose input/outpu t to external ics. each gpio module supports up to 32 bits of i/o. gpmi general purpose memory int erface the gpmi module supports up to 8x nand device s and 62-bit ecc encryption/decryption for nand fl ash controller (gpmi2). gpmi supports separate dma channe ls for each nand device. gpt1 gpt2 gpt3 gpt4 gpt5 gpt6 general purpose timer each gpt is a 32-bit free-running or se t-and-forget mode timer with programmable prescaler and compar e and capture register. a time r counter value can be captured using an e xternal event a nd can be config ured to trigger a capture event on either the leading or t railing edges of an input pulse. when the timer is configured to operate in set-and-forg et mode, it is capable of providing precise interrupts at re gular intervals with minimal processor intervention. the count er has output compare logic to provide the status and interrupt at comparis on. this timer ca n be configure d to run either on an external cloc k or on an internal clock. gpu3d graphics processing unit-3d t he gpu3d provide s hardware acc eleration for 3d g raphics algorithms with sufficient processor power t o run desktop quality interact ive graphics applications on displays. hdmi tx hdmi tx interface the hdm i module provides an hdmi standa rd interface port to an hdmi 2.0a-compliant display. i2c1 i2c2 i2c3 i2c4 i 2 c interface i 2 c provides serial interface for external devices. iomuxc iomux control this module en ables flexible i/o multiplexin g. each io pad has a default as well as several alternate f unctions. the alte rnate functions are software configurable. lcdif lcd interface the lcdif is a general purpose display contro ller used to drive a wide range of display devices vary ing in size and capability. table 3. i.mx 8m dual / 8m quadlit e / 8m quad modules list (cont inued) block mnemonic block na me brief description
i.mx 8m dual / 8m quadlite / 8m quad applications processors da ta sheet for consumer pr oducts, rev. 0.1, 05/2018 10 nxp semiconductors modules list mipi csi2 (four-lane) mipi camer a serial interface this module pr ovides two four-lane mipi camera serial interfaces, each of them can operate up to a maximum bit rate of 1.5 gbps. mipi dsi (four-lane) mipi displ ay serial interface this module pr ovides a four-lane mipi display serial interface operating up to a maximum bit ra te of 1.5 gbps. ocotp_ctrl otp controller the on-c hip otp controller (ocotp_ctrl) provides an interface for reading, programming, and/or ove rriding identification and cont rol information stored in on-chip f use elements. t he module support s electrically programmable poly f uses (efuses). the ocotp_ctrl a lso provides a set of volat ile software-accessi ble signals that can be used for software control of hardware el ements, not requiring non volati lity. the ocotp_ctrl provides the primary user-visible mechanism for interfacing with on-chip fuse el ements. among the uses for the fuses are unique chip identifiers, mask re vision numbers, cryptographic k eys, jtag secure mode, boot chara cteristics, and vari ous control signals requiring permanent non volatility. ocram on-chip memory controller the on-chip memory controller (oc ram) module is d esigned as an interface between the systems axi bus and the internal (on-chi p) sram memory module. in i.mx 8m dual / 8m q uadlite / 8m quad processors, the ocram i s used for controlling the 128 kb mu ltimedia ram through a 64-bit axi bus. pcie1 pcie2 2x pci express 2.0 the pcie ip pr ovides pci express gen 2.0 func tionality. pmu power management unit integrated power management unit. used to provide power to various soc domains. pwm1 pwm2 pwm3 pwm4 pulse width modulation the pulse -width modulator (pwm) has a 16- bit counter and is optimized to generate sound from stored sample audio images. i t can also gen erate tones. it uses 16-bit resolution and a 4x16 data fifo to generate soun d. qspi quad spi the quad spi module ac ts as an interfa ce to externa l serial flash devices. this module contains the following features: ? flexible sequence engine to support vari ous flash vendor devi ces ? single pad/dual pad/quad pad mode of operation ? single data rate/double data rate mode of operation ? parallel flash mode ? dma support ? memory mapped re ad access to connected flash devices ? multi master access with prior ity and flexible and configurab le buffer for each master sai1 sai2 sai3 sai4 sai5 sai6 synchronous audio interface the sai module provi des a synchronou s audio interface (sai) that supports full duplex serial inte rfaces with fra me synchronizati on, such as i2s, ac97, tdm, and codec/dsp interfaces. table 3. i.mx 8m dual / 8m quadlit e / 8m quad modules list (cont inued) block mnemonic block na me brief description
modules list i.mx 8m dual / 8m quadlite / 8m quad applications processors da ta sheet for consumer pr oducts, rev. 0.1, 05/2018 nxp semiconductors 11 sdma smart direct memory access the sdma is a multichannel flexib le dma engine. it helps in maximizing system performance by offloadi ng the various cor es in dynamic d ata routing. it has the following features: ? powered by a 16-bit instru ction-set micro-risc engine ? multi channel dma supporting up to 32 time -division multiplex ed dma channels ? 48 events with total flexibility to trigge r any combination o f channels ? memory accesses including li near, fifo, and 2d addressing ? shared peripherals between arm and sdma ? very fast context-switching with 2-level priority based preem ptive multi tasking ? dma units with auto-flus h and prefetch capability ? flexible address ma nagement for dma tra nsfers (increment, decrement, and no address change s on source and de stination add ress) ? dma ports can handle unidirectional and bidirectional flows ( copy mode) ? up to 8-word buffer for confi gurable burst tra nsfers for emiv 2.5 ? support of byte-swappi ng and crc calculations ? library of scripts a nd api is available sjc secure jtag controller the sjc provides jtag interface (desig ned to be compatible with jtag tap standards) to internal logic. the i.mx 8m dua l / 8m quadlit e / 8m quad of processors use jtag por t for production, testing, and s ystem debugging. additionally, the sjc provides bsr (boundary scan re gister) standard support, designed to be compatible with ieee 1149.1 an d ieee 1149.6 standards. the jtag port must be accessible during platform i nitial labora tory bring-up, for manufacturing te sts and troubleshooting, as well as for software debugging by authorized e ntities. the sjc of the i.mx 8m dual / 8m quadlite / 8m quad incorporates three sec urity modes for pro tecting against unauthorized a ccesses. modes are se lected through efuse configuration. snvs secure non-volatile storage secure non-volatil e storage, inc luding secure real time clock, security state machine, and master key control. spdif1 spdif2 sony philips digita l interconnect format a standard audio file transfer fo rmat, developed jointly by the sony and phillips corporations . it supports transmitt er and receiver fun ctionality. tempsensor temperature sensor temperature sensor tzasc trust-zone address space controller the tzasc (tzc-380 by arm) prov ides security address region con trol functions required for intended a pplication. it is used on the path to the dram controller. uart1 uart2 uart3 uart4 uart interface each of the uartv2 modules supports the following serial data transmit/receive protocol s and configurations: ? 7- or 8-bit data words, 1 or 2 stop bits, programmable parity (even, odd, or none) ? programmable baud rates up to 4 mbps. this is a higher max ba ud rate relative to the 1.875 mhz, which is stated by the tia/eia-232-f standard. ? 32-byte fifo on tx and 32 half-word fifo on rx supporting aut o-baud table 3. i.mx 8m dual / 8m quadlit e / 8m quad modules list (cont inued) block mnemonic block na me brief description
i.mx 8m dual / 8m quadlite / 8m quad applications processors da ta sheet for consumer pr oducts, rev. 0.1, 05/2018 12 nxp semiconductors modules list 2.1 recommended connections for unused interfaces the recommended connections for unused analog interfaces can be found in the section, unused input/output terminations, in t he hardware development guide f or the device. usdhc1 usdhc2 sd/mmc and sdxc enhanced multi-media card / secure digital host controller the i.mx 8m dual / 8m quadlite / 8m quad soc characteristics: all the mmc/sd/sdio controller ips are based on the usdhc ip. t hey are designed to support: ? sd/sdio standard , up to version 3.0. ? mmc standard, up to version 5.0. ? 1.8 v and 3.3 v operation, b ut do not support 1.2 v operation . ? 1-bit/4-bit sd and sdio mode s, 1-bit/4-bit/8-bit mmc mode. one usdhc controller (sd1) can support up to an 8-bit interface , the other controller (sd2) ca n only support up to a 4-bit interface. usb 3.0/2.0 2x usb 3.0/ 2.0 controllers and phys two usb controllers and phys tha t support usb 3.0 and usb 2.0. each usb instance contains: ? usb 3.0 core, which can ope rate in both 3. 0 and 2.0 mode vpu video processing unit a high pe rforming video pr ocessing unit (vpu), which covers many sd-level and hd-level video decoders. see the i.mx 8m dual / 8m quadlite / 8m quad applicati ons processor reference manual (imx8mdqlqrm) for a c omplete list of the vpus decoding and encoding ca pabilities. wdog1 wdog2 wdog3 watchdog the watchdog (wdog) time r supports two comparison point s during each counting period. each of the com parison points is configurable to evoke an interrupt to the arm core, and a second poi nt evokes an externa l event on the wdog line. xtalosc crystal oscillator interfa ce the xtalosc module enables c onnectivity to an external crystal oscillator device. table 3. i.mx 8m dual / 8m quadlit e / 8m quad modules list (cont inued) block mnemonic block na me brief description
electrical characteristics i.mx 8m dual / 8m quadlite / 8m quad applications processors da ta sheet for consumer pr oducts, rev. 0.1, 05/2018 nxp semiconductors 13 3 electrical characteristics this section provides the device and module-level electrical ch aracteristics for the i.mx 8m dual / 8m quadlite / 8m quad processors. 3.1 chip-level conditions this section provides the device-l evel electrical characteristi cs for the ic. see table 4 for a quick reference to the individual ta bles and sections. 3.1.1 absolute maximum ratings caution stresses beyond those listed under table 5 may affect reliability or cause permanent damage to the device. t hese are stress ratings only. functional operation of the device at thes e or any other conditions beyond those indicated in the opera ting ranges or parameters tables is not i mplied. table 4. i.mx 8m dual / 8m quadlite / 8m quad chip-level conditi ons for these characterist ics, topic appears absolute maximum ratings on page 13 fpbga package thermal resistance on page 14 operating ranges on page 15 external clock sources on page 17 maximum supply currents on page 18 power modes on page 19 usb phy suspend current consumption on page 22 table 5. absolute maximum ratings parameter description symbol min max unit notes core supply voltages vdd_arm vdd_soc 0 1.1 v 1.1 v is for vdd_arm overdrive power supply for gpu vdd_gpu 0 1.1 v 1.1 v is for overdrive power supply for vpu vdd_vpu 0 1.1 v nominal mode 0 1.1 v overdrive mode
i.mx 8m dual / 8m quadlite / 8m quad applications processors da ta sheet for consumer pr oducts, rev. 0.1, 05/2018 14 nxp semiconductors electrical characteristics 3.1.2 thermal resistance 3.1.2.1 fpbga package thermal resistance table 6 displays the thermal resistance data. gpio supply voltage nvcc_jtag, nvccgpio1, nvcc_ent, nvcc_sd1, nvcc_sd2, nvcc_nand, nvcc_sa1, nvcc_sai2, nvcc_sai3, nvcc_sai5, nvcc_ecspi, nvcc_i2c, nvcc_uart 0 3.6 v 1.8 v mode/3.3 v mode snvs io supply voltage nv cc_snvs 0 3.6 v 3.3 v mode only vdd_snvs supply voltage vdd_snvs 0 0.99 v usb high supply voltage usb1_vdd33, usb1_vph, usb2_vdd33, usb2_vph 03.63v usb_vbus input detected usb1_vbus, usb2_vbus 05.25v input voltage on usb*_dp, usb*_dn pins usb1_dp/usb1_dn usb2_dp/usb2_dn 0 usb1_vdd33 usb2_vdd33 v input/output voltage range v in /v out 0 ovdd 1 +0.3 v esd damage immunity: v esd v ? human body model (hbm) ? charge device model (cdm) 2000 500 storage temperature range t storage C40 150 o c 1 ovdd is the i/o s upply voltage. table 6. thermal resistance data rating test conditions symbol 17 x 17 pkg value unit junction to ambient 1 1 junction temperature is a functio n of die size, on-chip power d issipation, package thermal resi stance, mounting site (board) t emperature, ambient temperature, air flow, power dissipation of other compo nents on the board, and boa rd thermal resistance. single-layer board (1s) ; natural convection 2 four-layer board (2s2p) ; natural convection 2 2 per jedec jesd51-2 with the si ngle layer board h orizontal. ther mal test board meets jedec specification for the specified pack age. r ja r ja bare die: 16.4 o c/w o c/w junction to ambient 1 single-layer board (1 s); airflow 200 ft/min 2,3 four-layer board (2s 2p); airflow 200 ft/min 2,3 r ja r ja bare die: 13.9 o c/w o c/w junction to board 1,4 r jb bare die: 4.6 o c/w junction to case 1,5 r jc bare die: 0.1 o c/w table 5. absolute maximum ratings (continued) parameter description symbol min max unit notes
electrical characteristics i.mx 8m dual / 8m quadlite / 8m quad applications processors da ta sheet for consumer pr oducts, rev. 0.1, 05/2018 nxp semiconductors 15 3.1.3 operating ranges table 7 provides the operating ranges of the i.mx 8m dual / 8m quadlit e / 8m quad processors. for details on the chip's power struc ture, see the power managemen t unit (pmu) chapter of the i.mx 8m dual / 8m quadlite / 8m quad applic ations processor reference manual (imx8mdqlqrm). 3 per jedec jesd51-6 wit h the board horizontal. 4 thermal resistance between the d ie and the printed circuit boar d per jedec jesd51-8. board tempe rature is measured on the top surface of the board near the package. 5 thermal resistance between the die and the case top surface as measured by the cold plate m ethod (mil spec-883 method 1012.1). table 7. operating ranges parameter description symbol min typ max 1 unit comment power supply for quad-a53 vdd_arm 0 .81 0.9 1.05 v nominal modethe ma ximum arm core frequency supported in this mode is 1000 mhz. 0.9 1.0 1.05 v overdrive modethe maximum arm core frequency supported in this mode is defined in table 2 . power supply for soc logic vdd_soc 0.81 0.9 0.99 v power supply for gpu vdd_gpu 0.81 0 .9 1.05 v nominal modethe maximum gpu frequency supported in this mode is 800 mhz. 0.9 1.0 1.05 v overdrive modethe maximum gpu frequency supported in this mode is 1 ghz. power supply for vpu vdd_vpu 0.81 0 .9 1.05 v nominal modethe maximum vpu frequency supported in this mode is 550/500/588 mhz. 0.9 1.0 1.05 v overdrive modethe maximum vpu g2/g1/axi bus frequency supported in this mode is 660/600/800 mhz. core voltage vdd_dram 0.81 0.9 1.0 5 v nominal modethe maximum dram working frequency supported in this mode is 933 mhz. 0.99 1.0 1.05 v overdriv e modethe maximum dram working frequency supported in this mode is 1600 mhz power supply analog domain vdda_1p8 1.62 1.8 1.98 v power for internal analog blocksmust matc h the range of voltages that the rechargeable backup battery supports. pll 1.8 v supply voltage vdda_dram 1.71 1.8 1.89 v backup battery supply range vdd_snvs 0.81 0.9 0.99 v
i.mx 8m dual / 8m quadlite / 8m quad applications processors da ta sheet for consumer pr oducts, rev. 0.1, 05/2018 16 nxp semiconductors electrical characteristics supply for 25 mhz crystal vdd_1p8_xtal_25m 1.6 1.8 1.98 v supply for 27 mhz crystal vdd_1p8_xtal_27m 1.6 1.8 1.98 v temperature sensor vdd _1p8_tsensor 1.6 1.8 1.98 v usb supply voltages usb1_vdd33/ usb1_vph 3.069 3.3 3.63 v this rail is for usb usb2_vdd33/ usb2_vph 3.069 3.3 3.63 v this rail is for usb usb1/2_dvdd 0.837 0.900 0.990 v 0.9 v supply for usb high speed operation usb1/2_vp 0.837 0.900 0.990 v 0.9 v supply for usb super speed operation usb1/2_vptx 0.837 0.900 0.990 v 0 .9 v supply for phy transmit ddr i/o supply voltage nvcc_dr am 1.06 1.10 1.17 v lpddr4 1.14 1.2 1.26 v ddr4 1.28 1.35 1.42 v ddr3l dram_vref 0.49 x nvcc_d ram 0.5 x nvcc_d ram 0.51 x nvcc_d ram v set to one-half nvcc_dram gpio supply voltages nvcc_jtag, nvcc_sd1, nvcc_sd2, nvcc_nand, nvcc_sai1, nvcc_sai2, nvcc_sai3, nvcc_sai5, nvcc_ecspi, nvcc_i2c, nvcc_uart 1.65, 3.0 1.8, 3.3 1.95, 3.6 v nvcc_enet 1.65, 2.25 3.0 1.8, 2.5 3.3 1.95, 2.75 3.6 v nvcc_gpio1 1.65 3.0 1.8, 3.3 1.95, 3.6 v power for gpio1_io00 ~ gpio1_io15 nvcc_snvs 3.0 3.3 3.6 v power for 3.3 v only hdmi supply voltage hdmi_avddclk 0.850 0.900 0.990 v 0.9 v supply for hdmi high speed clock hdmi_avddio 1.700 1.800 1.900 v 1.8 v supply for hdmi bias and pll hdmi_avddcore 0.850 0.900 0.990 v 0.9 v supply for hdmi analog table 7. operating ranges (continued) parameter description symbol min typ max 1 unit comment
electrical characteristics i.mx 8m dual / 8m quadlite / 8m quad applications processors da ta sheet for consumer pr oducts, rev. 0.1, 05/2018 nxp semiconductors 17 3.1.4 external clock sources a 25 mhz oscillator is used as t he primary clock source for the plls to generate the clock for cpu, bus, and high-speed interfaces. for fr actional plls, the 25 mhz cloc k from the oscillator can be directly used as the pll reference clock. a 27 mhz oscillator is used as th e reference clock for hdmi phy . also it can be used as the alternative source for the fractional plls. a 32 khz clock input pin is used a s the rtc clock source. it is expected to be suppl ied by an external 32.768 khz oscillator. when an external rtc clock input is not present, the 32 khz clock for internal logic is generated by the 25 mhz oscillat or. the frequency of the int ernal 32 khz clock will be 31.25 khz. two pairs of differential cloc k inputs, named as clk1p and clk1 n, can be used as the reference clock for the pll. this is mainly us ed for a high-speed clock input d uring testing. four clock inputs to the ccm from normal gpio pads via iomux ca n be used as the clock sources in the ccm. table 8 shows the interface fr equency requirements. mipi supply voltage mipi_vdda 0.81 0 .9/1.0 1.1 v analog core power su pply mipi_vddha 1.62 1.8 1.98 v analog io power supply mipi_vdd 0.81 0.9/1.0 1.1 v d igital core power supply mipi_vddpll 0.81 0.9/1.0 1.1 v analog supply for mipi pll voltage rails supplied from 1.8 v phy pcie_vph 1.674 3.069 1.8 3.3 1.98 3.63 v supplied from pmic pcie_vp, pcie_vptx 0.837 0.9 0.99 v supplied from pmic temperature sensor accuracy t delta 3 c typical accura cy over the range C40c to 125c fuse power efuse_vqps 1.71 1.8 1.98 v power supply for internal use junction temperature, consumer t j 0+95 o csee table 2 for complet e list of junction temperature capabilities. 1 applying the maximum voltage res ults in maximum power consumpti on and heat generation. a voltage set point = (vmin + the suppl y tolerance) is recomme nded. this result in an optimized power/sp eed ratio. table 8. external inp ut clock frequency parameter description symbol min typ max unit rtc 1,2 1 external oscillator or a crystal with internal oscillator ampli fier. f ckil 32.768 3 khz xtali_25m/xtalo_25m 2 f xtal 20 25 40 mhz xtali_27m/xtalo_27m 2 f xtal 20 27 40 mhz table 7. operating ranges (continued) parameter description symbol min typ max 1 unit comment
i.mx 8m dual / 8m quadlite / 8m quad applications processors da ta sheet for consumer pr oducts, rev. 0.1, 05/2018 18 nxp semiconductors electrical characteristics the typical values shown in table 8 are required for use with nxp b sps to ensure precise time keep ing and usb operation. for rtc operation, two clock sources are ava ilable.the decision of choosing a clock source should be made based on real-time cl ock use and precisio n timeout. 3.1.5 maximum supply currents table 9 represents the maximum momenta ry current trans ients on power li nes and should be used for power supply selection. maximum c urrents are high er by far than the average power consumption of typ- ical use cases. 2 the required frequency stability of this clock source is applic ation dependent. 3 recommended nominal frequency 32.768 khz. table 9. maximum supply currents 1 power rail max current unit vdd_arm 384 to 2410 1 ma vdd_soc 1400 to 1870 1 ma vdd_gpu 0 to 2040 1 ma vdd_vpu 0 to 610 1 ma vdd_dram 600 to 870 1 ma vdda_0p9 50 ma vdda_1p8 20 ma vdda_dram 30 ma vdd_snvs 5ma nvcc_snvs 5ma nvcc_ i max = n x c x v x (0.5 x f) where: nnumber of io pins s upplied by the power line cequivalent exter nal capacitive load vio voltage (0.5 x f)data change rate. up to 0.5 of the clock rate (f). in this equation, i max is in amps, c in farads, v in volts, and f in hertz. nvcc_dram 375 to 750 1 ma dram_vfef 10 ma usb1_dvdd 9.2 ma usb2_dvdd 9.2 ma usb1_vp 35.7 ma usb2_vp 35.7 ma usb1_vptx 21.2 ma
electrical characteristics i.mx 8m dual / 8m quadlite / 8m quad applications processors da ta sheet for consumer pr oducts, rev. 0.1, 05/2018 nxp semiconductors 19 3.1.6 power modes the i.mx 8m dual / 8m quadlite / 8m quad processors support the following power modes: ? run mode: all external power rails are on, cpu is active and r unning; other internal modules can be on/off based on application. ? idle mode: when there is no thread running and all high-speed devices are not active, the cpu can automatically enter this mode . the cpu can be in the power- gated state but with l2 data retained, dram and the bus clock are reduced. most of the inter nal logic is clock gated but still remains powered. the m4 core can remain running. compared with run mode, all the external power rails from the pmic remai n the same, and most of the modu les still remain in their state. ? deep sleep mode (dsm): the most efficient power saving mode wh ere all the clocks are off and all the unnecessary power supplies are off. usb2_vptx 21.2 ma usb1_vdd33 24.5 ma usb2_vdd33 24.5 ma usb1_vph 20.3 ma usb2_vph 20.3 ma pcie_vp (pcie1) 38.1 ma pcie_vp (pcie2) 38.1 ma pcie_vph (pcie1) 43 ma pcie_vph (pcie2) 43 ma pcie_vptx (pcie1) 14.3 ma pcie_vptx (pcie2) 14.3 ma hdmi_avddclk 95.89 ma hdmi_avddcore hdmi_avddio 6.551 ma mipi_vdda (dsi) 17.1 ma mipi_vddha (dsi) 4.2 ma mipi_vdd (dsi) 14.4 ma mipi_vddpll (dsi) 3.8 ma mipi_vdda (csi1/2) 18.79 ma mipi_vddha (csi1/2) 2.97 ma efuse_vqps 96.35 ma 1 use case dependent table 9. maximum supply currents 1 (continued) power rail max current unit
i.mx 8m dual / 8m quadlite / 8m quad applications processors da ta sheet for consumer pr oducts, rev. 0.1, 05/2018 20 nxp semiconductors electrical characteristics ? snvs mode: this mode is als o called rtc mode. only the power f or the snvs domain remains on to keep rtc and snvs logic alive. ? off mode: all power rails are off. table 11 summarizes the external power supply states in all the power m odes. table 10. chip power in different lp mode mode supply max. 1 1 all the power numbers defined in the table are ba sed on typical silicon at 25 o c. use case dependent unit snvs vdd_snvs (1.0 v) 1.39 ma nvcc_snvs (3.6 v) 4.25 total 2 2 sum of the liste d supply rails. 17 mw deep sleep mode (dsm) vdd_soc (1.0 v) 148.50 ma vdda_1p8 (2.0 v) 12.82 vdda_0p9 (1.0 v) 0.30 vdda_dram (1.8 v) 0.50 vdd_snvs (1.0 v) 0.25 nvcc_snvs (3.3 v) 4.80 nvcc_dram (1.17 v) 4.51 total 2 197 mw idle vdd_arm (1.0 v) 152.10 ma vdd_soc (1.0 v) 132.90 vdd_dram (1.0 v) 44.10 vdda_1p8 (2.0 v) 13.53 vdda_0p9 (1.0 v) 0.30 vdda_dram (1.8 v) 1.32 vdd_snvs (1.0 v) 0.25 nvcc_snvs (3.3 v) 4.34 nvcc_dram (1.17 v) 13.12 total 2 389 mw run total 1 to 4 mw table 11. the power supply states power rail off snvs suspend idle run vdd_arm off off off on on vdd_soc off off on on on
electrical characteristics i.mx 8m dual / 8m quadlite / 8m quad applications processors da ta sheet for consumer pr oducts, rev. 0.1, 05/2018 nxp semiconductors 21 vdd_gpu off off off off on/off vdd_vpu off off off off on/off vdd_dram off off off on on vdda_0p9 off off on on on vdda_1p8 off off on on on vdda_dram off off on on on vdd_snvs off on on on on nvcc_snvs off on on on on nvcc_ off off on on on nvcc_dram off off on on on dram_vref off off off on on table 11. the power supply states (continued) power rail off snvs suspend idle run
i.mx 8m dual / 8m quadlite / 8m quad applications processors da ta sheet for consumer pr oducts, rev. 0.1, 05/2018 22 nxp semiconductors electrical characteristics 3.1.7 usb phy suspend current consumption 3.1.7.1 low power suspend mode the vbus valid comparators and t heir associated bandgap circuit s are enabled by default. table 12 shows the usb inte rface current consump tion in suspend mode wit h default settings. 3.1.7.2 power-down modes table 13 shows the usb inte rface current consumpt ion with only the otg block powered down. in power-down mode, everythi ng is powered down, including the u sb_vbus valid comparators and their associated bandgap c ircuity in typical condition. table 14 shows the usb interface current consumption in power-down mode. 3.1.8 pcie phy 2.1 dc electrical characteristics table 12. usb phy current consumption in suspend mode 1 1 low power suspend is enabled by setting usbx_portsc1 [phcd]=1 [ clock disable (plpscd)]. usb1_vdd33 usb2_vdd33 current 154 ? 154 ? table 13. usb phy current consumption in sleep mode 1 1 vbus valid comparators can be di sabled through software by sett ing usbnc_otg*_phy _cfg2[otgdisable0] to 1. this signal powers down only the vbus valid c omparator, and does not contro l power to the session valid co mparator, adp probe and sense comparators, or id detection circuitry. usb1_vdd33 usb2_vd33 current 520 ? 520 ? table 14. usb phy current con sumption in power-down mode 1 1 the vbus valid comparators and their associated bandgap circuit s can be disabled thr ough software by setting usbnc_otg*_phy_cfg2[otgdisable0] to 1 and usbnc_otg*_phy_cfg2[d rvvbus0] to 0, respectively. usb1_vdd33 usb2_vdd33 current 146 ? 146 ? table 15. pcie recommende d operating conditions parameter description min max unit pcie_vp low power supply voltag e for phy core 0.837 0.99 v pcie_vptx phy transmit supply 0.837 0.99 pcie_vph high power supply volt age for phy core 1.8 1.674 1.98 3.3 3.069 3.63
electrical characteristics i.mx 8m dual / 8m quadlite / 8m quad applications processors da ta sheet for consumer pr oducts, rev. 0.1, 05/2018 nxp semiconductors 23 note: v dd should have no more t han 40 mvpp ac power supply noise superim posed on the high power supply voltage for the phy core (1.8 v nominal dc value). at the same time, vdd should have no more than 20 mvpp ac power suppl y noise superimpos ed on the low power supply voltage for the phy co re (1.0 v nominal value or 1 .1 v overdrive dc value). the power supply voltage variati on for the phy core should have less than 5% including the boa rd-level power supply variation and on-chip power supply variation due to the finite imp edances in the pack age. t a commercial temperature range 0 70 c t j simulation junction temperature range -40 125 c table 16. pcie dc elect rical characteristics parameter description min typ max unit pcie1_vp, pcie2_vp power supply voltage 0.9 - 7% 0.9 0.9 + 10% v pd power consumption normal 40 mw partial mode 27 mw slumber mode 7 mw full powerdown 0.2 mw table 17. pcie phy high -speed characteristics high speed i/o characteristics description symbol speed min. typ. max. unit unit interval ui 2.5 gbps 400 ps 5.0 gbps 200 tx serial output rise time (20% to 80%) t txrise 2.5 gbps 100 ps 5.0 gbps 100 tx serial output fall time (80% to 20%) t txfall 2.5 gbps 100 ps 5.0 gbps 100 tx serial data output vo ltage (differential, pkCpk) v tx 2.5 gbps 800 1100 mvpCp 5.0 gbps 600 900 pcie tx deterministic jitter < 1.5 mhz trj 2.5 gbps 3 ps, rms 5.0 gbps 3 pcie tx deterministic jitter > 1 .5 mhz tdj 2.5 gbps 20 ps, pkCpk 5.0 gbps 10 table 15. pcie recommended opera ting conditions (continued) parameter description min max unit
i.mx 8m dual / 8m quadlite / 8m quad applications processors da ta sheet for consumer pr oducts, rev. 0.1, 05/2018 24 nxp semiconductors electrical characteristics pcie phy interface is compliant with pcie express gen2. 3.2 power supplies requirements and restrictions the system design must comply w ith power-up sequence, power-dow n sequence, and steady state guidelines as described in this section to guarantee the reliab le operation of the devi ce. any deviation from these sequences may resul t in the following situations: ? excessive current during power-up phase ? prevention of the de vice from booting ? irreversible damage to the pro cessor (worst-case scenario) 3.2.1 power-up sequence the i.mx 8m dual / 8m quadlite / 8m quad processors have the fo llowing power-up sequence requirements: ? turn on nvcc_snvs ? turn on vdd_snvs ? rtc_reset_b release ? turn on vdd_soc and vdda_0p9 rx serial data input volta ge (differential pkCpk) v rx 2.5 gbps 120 1200 mvpCp 5.0 gbps 120 1200 table 18. pcie phy refe rence clock timing requirements (vp is pi e_vp, 0.9 v power supply) symbol parameter min. typ. max. unit condition fref_offset reference clock frequency offset -300 30 ppm djref_clk reference clock cycle to cycle jitter 35 ps dj across a ll frequencies dcref_clk duty cycle 40 60 % vcmref_clk common mode input l evel 0 vp v differential inputs vdref_clk differentia l input swing -0.3 v pp differential inputs volref_clk single-ended input logi c low -0.3 -0.3 v if single-ended input is used. vohref_clk single-ended input logi c high vp - 0.3 vp + 0.3 v if sin gle-ended input is used. swref_clk input edge rate v/ns ref_clk_skew reference clock skew () 200 ps table 17. pcie phy high-speed characteristics (continued) high speed i/o characteristics description symbol speed min. typ. max. unit
electrical characteristics i.mx 8m dual / 8m quadlite / 8m quad applications processors da ta sheet for consumer pr oducts, rev. 0.1, 05/2018 nxp semiconductors 25 ? turn on vdd_arm, vdd_gpu, vdd_vpu , and vdd_dram (no sequence b etween these four rails) ? turn on vdda_1p8_xxx, vdda _dram (no sequence between these rai ls) ? turn on nvcc_xxx and nvcc_dram (no sequence between these rail s) ? por_b release (it should be a sserted during the entire power u p sequence) if the gpu/vpu is not used during the rom boot sequence, vdd_gp u/vdd_vpu can stay off to reduce the power during boot, and then t urned on by software afterward s. during the chip power up, the power of the pcie phy, usb phy, h dmi phy, and mipi phy could stay off. after chip power up, the power of these phys should be tur ned on. if any of the phy power are turned on during the power up sequence, the p or_b can be released afte r the phy power is stable. 3.2.2 power-down sequence the i.mx 8m dual / 8m quadlite / 8m quad processors have the fo llowing power-down sequence requirements: ? turn off nvcc_snvs and vdd_snvs last ? turn off vdd_soc after the othe r power rails or at the same ti me as other rails ? no sequence for other power rails during power down 3.2.3 power supplies usage i/o pins should not be externally driven while the i/o power su pply for the pin (nvcc_xxx) is off. this can cause internal latch-up and m alfunctions due to reverse cur rent flows. for infor mation about the i/o power supply of each pin, see power rail columns in the pin l ist tables of section 5, package information and contact assignments. table 19 lists the modules in each power domain. table 19. the modules in the power domains power domain modules in the domain vdd_arm arm a53 vdd_gpu gc7000l gpu vdd_vpu g1 and g2 vpu vdd_dram dram controller and phy vdd_snvs snvs_lp vdd_soc all the other modules
i.mx 8m dual / 8m quadlite / 8m quad applications processors da ta sheet for consumer pr oducts, rev. 0.1, 05/2018 26 nxp semiconductors electrical characteristics 3.3 pll electrical characteristics table 20. pll electrical parameters pll type parameter value audio_pll1 clock output range 650 mhz ~ 1.3 ghz reference clock 25 mhz lock time 50 s jitter 1% of output period, 50 ps audio_pll2 clock output range 650 mhz ~ 1.3 ghz reference clock 25 mhz lock time 50 s jitter 1% of output period, 50 ps video_pll1 clock outpu t range 650 mhz ~ 1.3 ghz reference clock 25 mhz lock time 50 s video_pll2 clock outpu t range 650 mhz ~ 1.3 ghz reference clock 25 mhz lock time 70 s sys_pll1 clock output range 800 mhz reference clock 25 mhz lock time 70 s sys_pll2 clock output range 1 ghz reference clock 25 mhz lock time 70 s sys_pll3 clock output range 600 mhz ~ 1ghz reference clock 25 mhz lock time 70 s arm_pll clock output range 800 mhz ~1.6 ghz reference clock 25 mhz lock time 50 s dram_pll clock output range 400 mhzC800 mhz reference clock 25 mhz lock time 70 s
electrical characteristics i.mx 8m dual / 8m quadlite / 8m quad applications processors da ta sheet for consumer pr oducts, rev. 0.1, 05/2018 nxp semiconductors 27 3.4 on-chip oscillators 3.4.1 osc25m and osc27m a 25 mhz oscillator is used as th e primary clock source for the plls to generate the clock for the cpu, bus, and high-speed interfaces. f or fractional plls, the 25 mhz clock from the oscillator can be used as the pll reference clock directly. a 27 mhz oscillator is used as th e reference clock for hdmi phy . it can also be used as the alternative source for the fractional plls. table 21 lists the electrical specificat ions of this oscillator when lo aded with an nx5032ga 40 mhz crystal unit at 40 mhz frequency. all values are valid only for the device tj operating specification of -40 o c to 125 o c. table 22 shows the transconductance sp ecification of the oscillator (in ma/v). gpu_pll clock output range 800 mhz ~1.6 ghz reference clock 25 mhz lock time 50 s vpu_pll clock output range 400 mhz ~ 800 mhz reference clock 25 mhz lock time 50 s table 21. electrical specifica tion of oscillator @ 1.8 v parameter min typ max unit voltage swing on external pin 1 1 the start-up time is dependent upon crystal characteristics, bo ard leakage, etc.; hi gh esr and excessive ca pacitive loads can cause long start-up time. 250 800 mv power consumption (analog supply rms current in osc mode) 2, 3 2 electrical parameters are subject to change. 3 maximum current is obse rved during startup. after oscillation i s stable, the current fro m hv supply comes down. 4ma start-up time 1, 2 2ms table 22. transconductance specification of oscillator gm_sel min max 111 10 25 table 20. pll electrical parameters (continued) pll type parameter value
i.mx 8m dual / 8m quadlite / 8m quad applications processors da ta sheet for consumer pr oducts, rev. 0.1, 05/2018 28 nxp semiconductors electrical characteristics table 23 shows the input clock specifications. table 24 shows core output c lock specification. table 25 shows vil/vih specification at extal. 3.5 i/o dc parameters this section includes the dc para meters of the following i/o ty pes: ? general purpose i/o (gpio) ? double data rate i/o (ddr) fo r lpddr4, ddr4, and ddr3l modes ? differential i/o (clkx) table 23. input clock specification parameter min typ max unit clock frequency in osc mode 20 40 mhz input clock frequency in bypass mode 50 mhz input clock rise/fa ll time in bypass mode 1ns input clock duty cycle in bypass mode 47.50 50 52.50 % table 24. core output clock specification parameter min typ max unit output clock frequency in osc mode 20 40 mhz output clock duty cycle in osc mode 45 50 55 % output clock frequency in bypass mode 50 mhz capacitive loading on outputs clock 150 500 ff output clock rise/fall time in bypass mode 0.10.5ns output clock duty cycle in bypass mode 40 50 60 % table 25. transconductance specification of oscillator parameter condition min max unit v ilextal v ref = 0.5 x avdd (xosc hv supply) 0v ref - 0.5 v v ihextal v ref + 0.5 avdd
electrical characteristics i.mx 8m dual / 8m quadlite / 8m quad applications processors da ta sheet for consumer pr oducts, rev. 0.1, 05/2018 nxp semiconductors 29 3.5.1 general purpose i/o (gpio) dc parameters table 26 shows dc parameters for g pio pads. the parameters in table 26 are guaranteed per the operating ranges in table 7 , unless otherwise noted. 3.5.2 ddr i/o dc electr ical characteristics the ddr i/o pads support lpddr 4, ddr4, and ddr3l operational m odes. the ddr memory controller (ddrmc) is designed t o be compatible with jedec-comp liant sdrams. table 26. gpio dc parameters parameter symbol test conditions min typ max unit high-level output voltage v oh (1.8 v) min v dd , i oh = C100 a, i oh = C2 ma v dd - 0.2, v dd - 0.45 v v oh (3.3 v) vdd - 0.2 2.4 v low-level output voltage v ol (1.8 v) min v dd , i oh = 100 a, i oh = 3 ma 0.2 0.2 x v dd v v ol (3.3 v) 0.2 0.4 v high-level input voltage v ih (1.8 v) ipp_lvttl_en = 0 0.7 x v dd v dd v v ih (3.3 v) ipp_lvttl_en = 1 2 v dd v v ih_1vcoms (3.3 v) ipp_lvttl_en = 0 0.7 x v dd v dd v low-level input voltage v il (1.8 v) ipp_lvttl_en = 0 0 0.2 x v dd v v il_emmc (1.8 v) ipp_lvttl_en = 0 0 0.35 x v dd v v il (3.3 v) ipp_lvttl_en = 1 0 0.8 v v il_emmc (3.3 v) ipp_lvttl_en = 0 0 0.25 x v dd v v il_1vcmos (3.3 v) ipp_lvttl_en = 0 0 0.2 x v dd v input hysteresis v hys (1.8 v) ipp_hys = 1 0.15 v v hys (3.3 v) ipp_hys = 1 0.2 v pull-up resistor 30 x 0.75 30 30 x 1.25 k pull-down resistor 95 x 0.75 95 95 x 1.25 k high level input current 1 1 the leakage limit for the following pins: hdmi_tx (several) is 200 a; hdmi_aux_n/p is 65 a; pmic_on_req is 60 a; pmic_stby_req is 80 a; rtc_reset_b is 60 a; onoff is 60 a; por_b is 60 a; and sd2_cd_b is 60 a. i ih -50 50 a low level input current 1 i il -50 50 a
i.mx 8m dual / 8m quadlite / 8m quad applications processors da ta sheet for consumer pr oducts, rev. 0.1, 05/2018 30 nxp semiconductors electrical characteristics ddrmc operation is contingent upon t he boards ddr design adher ence to the ddr design and layout requirements stated in the hard ware development guide for the i .mx 8m dual / 8m quadlite / 8m quad application processor. table 27. dc input logic level characteristics symbol min max unit dc input logic high 1 1 it is the relati onship of the v ddq of the driving device and the v ref of the receiving device that de termines noise margins. however , in the case of v ih (dc) max (that is, input overdrive), i t is the v ddq of the receiving device that is referenced. v ih(dc) v ref +100 mv dc input logic low v il(dc) v ref C100 table 28. output dc current drive characteristics symbol min max unit output minimum source dc current 1 1 when dds = [111] and without zq calibration. i oh (dc) C4 ma output minimum s ink dc current i ol (dc) 4 ma dc output high voltage(i oh = C0.1ma) ,2 2 the values of v oh and v ol are valid only for 1.2 v range. v oh 0.9 x v ddq v dc output low voltage(i ol = 0.1ma) , v ol 0.1 x v ddq v table 29. input dc current 1 1 the leakage limit for the following pins: dram_ac00, dram_ac01, dram_ac20, and dram_ac21 are 300 a; dram_reset_n is 200 a. characteristics symbol min max unit high level input current 2,3 2 the values of v oh and v ol are valid only for 1.2 v range. 3 driver hi-z and input power-down (pd = high) i ih C40 40 a low level input current , i il C40 40 a
electrical characteristics i.mx 8m dual / 8m quadlite / 8m quad applications processors da ta sheet for consumer pr oducts, rev. 0.1, 05/2018 nxp semiconductors 31 3.5.2.1 lpddr4 mode i/o dc parameters 3.5.3 differential i/o port (clkx_p/n) the clock i/o interface is desi gned to be compatible with tia/e ia 644-a standard. see tia/eia standard 644-a, electrical characteristics of low voltage differential signali ng (lvds) interface circuits (2001) , for details. the clk1_p/clk1_n is input only, w hile clk2_p/clk2_n is output only. 3.6 i/o ac parameters this section includes the ac para meters of the following i/o ty pes: ? general purpose i/o (gpio) ? double data rate i/ o (ddr) for ddr3l/ddr4/lpddr4 modes ? differential i/o (clkx) the gpio and ddr i/o load circu it and output transition time wa veforms are shown in figure 3 and figure 4 . table 30. lpddr4 i/o dc electrical parameters parameters symbol test conditions min max unit high-level output voltage voh ioh= -0.1 ma 0.9 x ovdd v low-level output voltage vol iol= 0.1 ma 0.1 x ovdd v input reference voltage vref 0.49 x ovdd 0.51 x ovdd v dc high-level input volta ge vih_dc vref + 0.100 ovdd v dc low-level input voltage vil_dc ovss vref C 0.100 v differential input logic high vih_diff 0.26 see note 1 1 the single-ended signals need to be within the respective limit s (vih(dc) max, vil(dc) min) for single-ended signals as well a s the limitations for overs hoot and undershoot. differential input logic lo w vil_diff see note -0.26 pull-up/pull-down impeda nce mismatch mmpupd C15 15 % 240 unit calibration resolution rres 10 keeper circuit resistance rkeep 110 175 k input current (no pull-up/down) i in vi = 0, vi = ovdd -2.5 2.5 a
i.mx 8m dual / 8m quadlite / 8m quad applications processors da ta sheet for consumer pr oducts, rev. 0.1, 05/2018 32 nxp semiconductors electrical characteristics figure 3. load circuit for output figure 4. output transition time waveform 3.6.1 general purpose i/o ac parameters this section presents the i/o ac parameters for gpio in differe nt modes. note that the fast or slow i/o behavior is determined by the a ppropriate contro l bits in the i omuxc control registers. table 31. maximum input cell delay time cell name max delay pad ?? y (ns) v dd = 1.62 v t = 125c wcs model v dd = 3.0v t = 125c wcs model pbijgtov36pud_mclamp_ lvgpio_ew 1.54 1.3 table 32. output cell delay time for fixed load parameter simulated cell delay a ?? pad (ns) vdd = 1.62 v, t = 125c vdd = 2.97 v, t = 125c dse[2:0] fsel[1:0] driver type cl = 15 pf cl = 15 pf 011 00 3 x slow slew 3.1 3.3 011 11 3 x fast slew 2.1 2.6 100 00 4 x slow slew 3.7 3.9 100 11 4 x fast slew 2.3 2.8 101 00 5 x slow slew 3.1 3.5 101 11 5 x fast slew 2.1 2.5 test point from output under test cl cl includes package, probe and fixture capacitance 0v ovdd 20% 80% 80% 20% tr tf output (at pad)
electrical characteristics i.mx 8m dual / 8m quadlite / 8m quad applications processors da ta sheet for consumer pr oducts, rev. 0.1, 05/2018 nxp semiconductors 33 3.6.2 clock i/o ac para metersclkx_n/clkx_p the differential output transi tion time waveform is shown in figure 5 . figure 5. differential lvds dri ver transition time waveform 111 00 7 x slow slew 2.9 3.1 111 11 7 x fast slew 1.8 2.3 table 33. maximum frequen cy of operation for input maximum frequency (mhz) vdd = 1.8 v, cl = 15 pf, fast vdd = 3.3 v, cl = 20 pf, fast 200 160 table 32. output cell delay time for fixed load (continued) parameter simulated cell delay a ?? pad (ns) vdd = 1.62 v, t = 125c vdd = 2.97 v, t = 125c dse[2:0] fsel[1:0] driver type cl = 15 pf cl = 15 pf
i.mx 8m dual / 8m quadlite / 8m quad applications processors da ta sheet for consumer pr oducts, rev. 0.1, 05/2018 34 nxp semiconductors electrical characteristics table 34 shows the ac parame ters for clock i/o. 3.7 output buffer impedance parameters this section defines the i/o imp edance parameters of the i.mx 8 m dual / 8m quadlite / 8m quad processors for the following i/o types: ? double data rate i/o (ddr) fo r lpddr4, ddr4, and ddr3l modes ? differential i/o (clkx) ? usb battery charger detection ope n-drain output (usb_otg1_chd_ b) note ddr i/o output driver impedance i s measured with long transmi ssion line of impedance ztl attache d to i/o pad and incident wave lau nched into transmission line. rpu/ rpd and ztl form a vo ltage divider that defines specific voltage of incident wa ve relative to o vdd. output driv er impedance is calculated from this voltage divider (see figure 6 ). table 34. i/o ac parameters of lvds pad symbol parameter test conditions min typ max unit notes tphld output differen tial propagation delay high to low rload = 1 00 between padp and padn, cload = 2pf, at 125 c, typ, 1.62 v ovdd, and 0.9 v vddi 0.92 ns 1 1 at typ, 125 c, 1.62 v ovdd, and 0. 9 v vddi. measurement levels are 50 - 50%. output diffe rential signa l measured. tplhd output differen tial propagation delay low to high 0.92 ttlh output transition time low to high 0.58 2 2 at typ, 125 c, 1.62 v ovdd, and 0. 9 v vddi. measurement levels are 20 - 80%. output diffe rential signal measured. tthl output transition time high to low 0.73 tphlr input differentia l propagation delay hi gh to low rload = 10 0 between padp and padn, at 125 c, typ, 1.62 v ovdd, and 0.9 v vddi 0.83 ns 3 3 at typ, 125 c, 1.62 v ovdd, and 0. 9 v vddi. measurement levels are 50 - 50%. tplhr input differentia l propagation delay low to high 0.83 ttx transmitter startup time ( ipp-obe low to high) 40 ns 4 4 tx startup time is defi ned as the time take n by transmitter for settling after its i pp_obe has been assert ed. it is to stabili ze the current reference. functionalit y is guaranteed only after the startup t ime. f operating frequency 600 1000 mhz
electrical characteristics i.mx 8m dual / 8m quadlite / 8m quad applications processors da ta sheet for consumer pr oducts, rev. 0.1, 05/2018 nxp semiconductors 35 figure 6. impedance matchi ng load for measurement ipp_do cload = 1p ztl w , l = 20 inches predriver pmos (rpu) nmos (rpd) pad ovdd ovss t,(ns) 0 u,(v) ovdd t,(ns) 0 vdd vin (do) vout (pad) u,(v) vref rpu = vovdd - vref1 vref1 x ztl rpd = x ztl vref2 vovdd - vref2 vref1 vref2
i.mx 8m dual / 8m quadlite / 8m quad applications processors da ta sheet for consumer pr oducts, rev. 0.1, 05/2018 36 nxp semiconductors electrical characteristics 3.7.1 ddr i/o output buffer impedance table 35 shows ddr i/o output buffer impeda nce of i.mx 8m dual / 8m qua dlite / 8m quad processors. note: 1. output driver imped ance is controlled across pvts using zq c alibration procedure. 2. calibration is done against 240 external reference resistor. 3. output driver impedance devia tion (calibration accuracy) is 5% (max/min impedance) across pvts. 3.7.2 differential i/o output buffer impedance the differential ccm interface is designed to be compatible wit h tia/eia 644-a standard. see, tia/eia standard 644-a, electrical characteristics of low voltage differential signali ng (lvds) interface circuits (2001) for details. 3.7.3 usb battery charger d etection driver impedance the usb_otg1_chd_b open-drai n output pin can be used to signal to power management and monitoring device results of usb battery charger detection rout ines for the usb_otg1 phy instance. use of this pin requires an ext ernal pullup resistor, for more information see table 5 . 3.8 system modules timing this section contains the timi ng and electrical parameters for the modules in each i.mx 8m dual / 8m quadlite / 8m quad processor. table 35. ddr i/o output buffer impedance parameter symbol test conditions dse (drive strength) typical unit nvcc_dram = 1.35 v (ddr3l) ddr_sel = 11 nvcc_dram = 1.2 v (ddr4) nvcc_dram = 1.1 v (lpddr4) ddr_sel = 10 output driver impedance rdrv 000000 hi-z hi-z hi-z 000010 240 240 240 000110 120 120 120 001010 80 80 80 001110 606060 011010 48 48 48 011110 404040 111010 34 34 34
electrical characteristics i.mx 8m dual / 8m quadlite / 8m quad applications processors da ta sheet for consumer pr oducts, rev. 0.1, 05/2018 nxp semiconductors 37 3.8.1 reset timings parameters figure 7 shows the reset timing and table 36 lists the timing parameters. figure 7. reset timing diagram 3.8.2 wdog reset ti ming parameters figure 8 shows the wdog reset timing and table 37 lists the timing parameters. figure 8. wdog x _b timing diagram note rtc_xtali is approximately 32 khz. rtc_xtali cycle is one period or approximately 30 m s. note wdog x _b output signals (for each o ne of the watchdog modules) do not have dedicated pins, but are muxe d out through the iomux. see t he iomuxc chapter of the i.mx 8m dual / 8m quadlite / 8m quad applications processor reference manual (imx8mdqlqrm) for detailed information. 3.9 external peripheral interface parameters the following subsections provide information on external perip heral interfaces. table 36. reset timing parameters id parameter min max unit cc1 duration of por_b to be qualified as valid. 1 rtc_xtali cycle table 37. wdog x _b timing parameters id parameter min max unit cc3 duration of wdog1_b assertion 1 rtc_xtali cycle por_b cc1 (input) wdog x _b cc3 (output)
i.mx 8m dual / 8m quadlite / 8m quad applications processors da ta sheet for consumer pr oducts, rev. 0.1, 05/2018 38 nxp semiconductors electrical characteristics 3.9.1 ecspi timing parameters this section describes the timi ng parameters of the ecspi block s. the ecspi have separate timing parameters for maste r and slave modes. 3.9.1.1 ecspi master mode timing figure 9 depicts the timing of ecspi in master mode. table 38 lists the ecspi master mode timing characteristics. figure 9. ecspi master mode timing diagram table 38. ecspi master mode timing parameters id parameter symbol min max unit cs1 ecspix_sclk cycle timeCread ecspix_sclk cycle timeCwrite t clk 43 15 ns cs2 ecspix_sclk high or low timeCread ecspix_sclk high or low timeCwrite t sw 21.5 7 ns cs3 ecspix_sclk rise or fall 1 1 see specific i/o ac parameters section 3.6, i/o ac parameters. t rise/fall ns cs4 ecspix_ss_b pulse width t cslh half ecspix_sclk period ns cs5 ecspix_ss_b lead t ime (cs setup time) t scs half ecspix_sclk period - 4 ns cs6 ecspix_ss_b lag t ime (cs hold time) t hcs half ecspix_sclk period - 2 ns cs7 ecspix_mosi propagation delay (c load =20pf) t pdmosi -1 1 ns cs8 ecspix_miso setup time t smiso 18 ns cs9 ecspix_miso hold time t hmiso 0ns cs10 rdy to ecspix_ss_b time 2 2 spi_rdy is sampled i nternally by ipg_clk and is asynchronous to all other cspi signals. t sdry 5ns cs7 cs2 cs2 cs4 cs6 cs5 cs8 cs9 ecspix_sclk ecspix_ss_b ecspix_mosi ecspix_miso ecspix_rdy_b cs10 cs3 cs3 cs1
electrical characteristics i.mx 8m dual / 8m quadlite / 8m quad applications processors da ta sheet for consumer pr oducts, rev. 0.1, 05/2018 nxp semiconductors 39 3.9.1.2 ecspi slave mode timing figure 10 depicts the timing of e cspi in slave mode. table 39 lists the ecspi slave mode timing characteristics. figure 10. ecspi slave mode timing diagram table 39. ecspi slave m ode timing parameters id parameter symbol min max unit cs1 ecspix_sclk cy cle timeCread ecspi_sclk cycle timeCwrite t clk 15 43 ns cs2 ecspix_sclk high or low timeCread ecspix_sclk high or low timeCwrite t sw 7 21.5 ns cs4 ecspix_ss_b pulse width t cslh half ecspix_sclk period ns cs5 ecspix_ss_b lead time (cs setup time) t scs 5ns cs6 ecspix_ss_b lag ti me (cs hold time) t hcs 5ns cs7 ecspix_mosi setup time t smosi 4ns cs8 ecspix_mosi hold time t hmosi 4ns cs9 ecspix_miso pr opagation delay (c load =20pf) t pdmiso 419ns cs1 cs7 cs8 cs2 cs2 cs4 cs6 cs5 cs9 ecspix_sclk ecspix_ss_b ecspix_miso ecspix_mosi
i.mx 8m dual / 8m quadlite / 8m quad applications processors da ta sheet for consumer pr oducts, rev. 0.1, 05/2018 40 nxp semiconductors electrical characteristics 3.9.2 ultra-high-speed sd/sdio/mmc host interface (usdhc) ac timing this section describes the elect rical information of the usdhc, which includes sd/emmc4.3 (single data rate) timing, emmc4.4/4.41 (dual data rate) timing and sdr104/5 0 (sd3.0) timing. 3.9.2.1 sd/emmc4.3 (single data rate) ac timing figure 11 depicts the timing of sd/emmc4.3, and table 40 lists the sd/emmc4.3 t iming characteristics. figure 11. sd/emmc4.3 timing table 40. sd/emmc4.3 interf ace timing specification id parameter symbols min max unit card input clock sd1 clock frequency (low speed) f pp 1 0 400 khz clock frequency (sd/sdio full speed/high speed) f pp 2 0 25/50 mhz clock frequency (mmc f ull speed/high speed) f pp 3 0 20/52 mhz clock frequency (iden tification mode) f od 100 400 khz sd2 clock low time t wl 7ns sd3 clock high time t wh 7ns sd4 clock rise time t tlh 3ns sd5 clock fall time t thl 3ns usdhc output/card inputs sd_cmd, sdx_datax (reference to clk) sd6 usdhc output delay t od 6.6 3.6 ns sd1 sd3 sd5 sd4 sd7 sdx_clk sd2 sd8 sd6 output from usdhc to card input from card to usdhc sdx_data[7:0] sdx_data[7:0]
electrical characteristics i.mx 8m dual / 8m quadlite / 8m quad applications processors da ta sheet for consumer pr oducts, rev. 0.1, 05/2018 nxp semiconductors 41 3.9.2.2 emmc4.4/4.41 (dual data rate) ac timing figure 12 depicts the ti ming of emmc4.4/4.41. table 41 lists the emmc4.4/4.41 timing characteristics. be aware that only data is sam pled on both edges of the clock ( not applicable to cmd). figure 12. emmc4.4/4.41 timing usdhc input/card outputs sd_cmd, sdx_datax (reference to clk) sd7 usdhc input setup time t isu 2.5 ns sd8 usdhc input hold time 4 t ih 1.5 ns 1 in low-speed mode, card clock mus t be lower than 400 khz, voltag e ranges from 2.7 to 3.6 v. 2 in normal (full) -speed mode for sd/sdio card, c lock frequency can be any valu e between 0 C 25 mhz. in high-speed mode, clock frequency can be a ny value between 0 C 50 mhz. 3 in normal (full) -speed mode for mmc card, clock frequency can be any value between 0 C 20 mhz. in high-speed mode, clock frequency can be a ny value between 0 C 52 mhz. 4 to satisfy hold timing, the delay difference between clock inpu t and cmd/data input m ust not exceed 2 ns. table 41. emmc4.4/4.41 interf ace timing s pecification id parameter symbols min max unit card input clock sd1 clock frequency (e mmc4.4/4.41 ddr) f pp 052mhz sd1 clock frequency (sd3.0 ddr) f pp 050mhz usdhc output / card inputs sd_cmd, sdx_datax (reference to clk) sd2 usdhc output delay t od 2.7 6.9 ns usdhc input / card outputs sd_cmd, sdx_datax (reference to clk) table 40. sd/emmc4.3 interface ti ming specification (continued) id parameter symbols min max unit sd1 sd2 sd3 output from esdhcv3 to card input from card to esdhcv3 sdx_data[7:0] sdx_clk sd4 sd2 ...... ...... sdx_data[7:0]
i.mx 8m dual / 8m quadlite / 8m quad applications processors da ta sheet for consumer pr oducts, rev. 0.1, 05/2018 42 nxp semiconductors electrical characteristics 3.9.2.3 hs400 ddr ac timing emmc5.0 only figure 13 depicts the timing of hs400 mode, and table 42 lists the hs400 timi ng characteristics. be aware that only data is sample d on both edges of the clock (not applicable to cmd). the cmd input/output timing for hs400 mode is the same as cmd input/out put timing for sdr104 mode. check sd5, sd6, and sd7 parameters in table 44 sdr50/sdr104 interface tim ing specification for cmd input/output timing for hs400 mode. figure 13. hs400 mode timing sd3 usdhc input setup time t isu 2.4 ns sd4 usdhc input hold time t ih 1.3 ns table 42. hs400 interface timing specification id parameter symbols min max unit card input clock sd1 clock frequency f pp 0 200 mhz sd2 clock low time t cl 0.46 x t clk 0.54 x t clk ns sd3 clock high time t ch 0.46 x t clk 0.54 x t clk ns usdhc output/card inputs d at (reference to sck) sd4 output skew from dat a of edge of sck t oskew1 0.45 ns sd5 output skew from e dge of sck to data t oskew2 0.45 ns usdhc input/card outputs dat (reference to strobe) table 41. emmc4.4/4.41 interface ti ming specificati on (continued ) id parameter symbols min max unit 6' 6' 6' 6' 6' 6&. 2xwsxwiurp 6wureh ,qsxwiurp x6'+&wrh00& h00&wrx6'+& '$7 '$7 '$7 '$7 '$7 '$7 6' 6' 6' 6'
electrical characteristics i.mx 8m dual / 8m quadlite / 8m quad applications processors da ta sheet for consumer pr oducts, rev. 0.1, 05/2018 nxp semiconductors 43 3.9.2.4 hs200 mode timing figure 14 depicts the timing of hs200 mode, and table 43 lists the hs200 tim ing characteristics. figure 14. hs200 mode timing iti sd6 usdhc input skew t rq 0.45 ns sd7 usdhc hold skew t rqh 0.45 ns table 43. hs200 interfa ce timing specification id parameter symbols min max unit card input clock sd1 clock frequency period t clk 5ns sd2 clock low time t cl 0.3 x t clk 0.7 x t clk ns sd3 clock high time t ch 0.3 x t clk 0.7 x t clk ns usdhc output/card inputs sd_cmd , sdx_datax in hs200 (reference to clk) sd5 usdhc output delay t od -1.6 1 ns usdhc input/card out puts sd_cmd, sdx_datax in hs200 (reference to clk) 1 1 hs200 is for 8 bits whil e sdr104 is for 4 bits. sd8 usdhc output data window t odw 0.5 x t clk ns table 42. hs400 interface timing specification (continued) id parameter symbols min max unit 6&. elwrxwsxwiurpx6'+&wrh00& elwlqsxwiurph00&wrx6'+& 6' 6'6' 6' 6' 6'
i.mx 8m dual / 8m quadlite / 8m quad applications processors da ta sheet for consumer pr oducts, rev. 0.1, 05/2018 44 nxp semiconductors electrical characteristics 3.9.2.5 sdr50/sdr104 ac timing figure 15 depicts the timing of sdr50/sdr104, and table 44 lists the sdr50/sdr104 timing characteristics. figure 15. sdr50/sdr104 timing 3.9.2.6 bus operation conditi on for 3.3 v and 1.8 v signaling signaling level of sd/emmc4.3 a nd emmc4.4/4.41 mode s is 3.3 v. signaling level of sdr104/sdr50 mode is 1.8 v. the dc parameters for the nvcc_sd1, nvcc_sd2 and nvcc_sd3 supplies are identical to those shown in table 26, "gpio dc parameters," on page 29 . table 44. sdr50/sdr104 interf ace timing specification id parameter symbols min max unit card input clock sd1 clock frequency period t clk 5ns sd2 clock low time t cl 0.46 x t clk 0.54 x t clk ns sd3 clock high time t ch 0.46 x t clk 0.54 x t clk ns usdhc output/card inputs sd_cmd, sdx_datax in sdr50 (reference to clk) sd4 usdhc output delay t od -3 1 ns usdhc output/card inputs sd_cmd, sdx_datax in sdr104 (reference to clk) sd5 usdhc output delay t od -1.6 1 ns usdhc input/card outputs sd_cmd, sdx_datax in ddr50 (reference to clk) sd6 usdhc input setup time t isu 2.4 ns sd7 usdhc input hold time t ih 1.4 ns usdhc input/card outputs sd_cmd, sdx_datax in sdr104 (reference to clk) 1 1 data window in sdr100 mode is variable. sd8 usdhc output data window t odw 0.5 x t clk ns sck 8-bit output from usdhc to emmc 8-bit input from emmc to usdhc sd8 sd7 sd6 sd4/sd5 sd2 sd3 sd1
electrical characteristics i.mx 8m dual / 8m quadlite / 8m quad applications processors da ta sheet for consumer pr oducts, rev. 0.1, 05/2018 nxp semiconductors 45 3.9.3 ethernet controller (enet) ac electrical specifications the following timing specs are defined at the chip i/o pin and must be translated a ppropriately to arrive at timing specs/constraints for the physical interface. 3.9.3.1 rmii mode timing in rmii mode, enet_clk is used as the ref_clk, which is a 50 mhz 50 ppm continuous reference clock. enet_rx_en is used as the enet_rx_en in rmii. other signals under rmii mode include enet_tx_en, enet_tx_data[1:0] , enet_rx_data[1:0] and enet_rx_er. figure 16 shows rmii mode timings. table 45 describes the timing parameters (m16Cm21) shown in the figure. figure 16. rmii mode signal timing diagram table 45. rmii signal timing id characteristic min. max. unit m16 enet_clk pulse width high 35% 65% enet_clk period m17 enet_clk pulse width low 35% 65% enet_clk period m18 enet_clk to enet0_txd[1:0 ], enet_tx_data invalid 4 ns m19 enet_clk to enet0_txd[1:0 ], enet_tx_data valid 15 ns m20 enet_rx_datad[1:0], enet_rx_ en(enet_rx_en), enet_rx_er to enet_clk setup 4 ns m21 enet_clk to enet_rx_datad[1:0] , enet_rx_en, enet_rx_er hold 2 ns enet_clk (input) enet_tx_en m16 m17 m18 m19 m20 m21 enet_rx_data[1:0] enet_tx_data (output) enet_rx_er enet_rx_en (input)
i.mx 8m dual / 8m quadlite / 8m quad applications processors da ta sheet for consumer pr oducts, rev. 0.1, 05/2018 46 nxp semiconductors electrical characteristics 3.9.3.2 rgmii signal switc hing specifications the following timing specifications meet the requirements for r gmii interfaces for a range of transceiver devices. figure 17. rgmii transmit sig nal timing di agram original table 46. rgmii signal switching specifications 1 1 the timings assume the f ollowing configuration: ddr_sel = (11)b dse (drive-strength) = (111)b symbol description min. max. unit t cyc 2 2 for 10 mbps and 100 mbps, t cyc will scale to 400 ns 40 ns and 40 ns 4 ns respectively. clock cycle duration 7.2 8.8 ns t skewt 3 3 for all versions of rgmii prior to 2.0; this implies that pc bo ard design will require clocks to be routed such that an additi onal trace delay of greater than 1.5 ns and less than 2.0 ns will be added to th e associated clock signal. for 10/100, the max value is unspeci fied. data to clock output ske w at transmitter -500 500 ps t skewr 3 data to clock input sk ew at receiver 1 2.6 ns duty_g 4 4 duty cycle may be stretched/shr unk during speed changes or whil e transitioning to a received packet's clo ck domain as long as minimum duty cycle is not violated and st retching occurs f or no more th an three tcyc of the lowest speed transiti oned between. duty cycle for gigabit 45 85 % duty_t 4 duty cycle for 10/100t 40 90 % tr/tf rise/fall time (20C80%) 0.98 ns 2'-))?48#attransmitter 2'-))?48$nnto 2'-))?48?#4, 2'-))?48#atreceiver 4skew4 48%. 48%22 4skew2
electrical characteristics i.mx 8m dual / 8m quadlite / 8m quad applications processors da ta sheet for consumer pr oducts, rev. 0.1, 05/2018 nxp semiconductors 47 figure 18. rgmii receive signa l timing diagram original figure 19. rgmii receive signal timing diagr am with internal del ay 3.9.4 general-purpose media interface (gpmi) timing the gmpi controller of the i.mx 8m dual / 8m quadlite / 8m quad processor is a flexible interface nand flash controller with 8-bi t data width, up to 200 mb/s i/o speed and individual chip select. it supports asynchronous timi ng mode, source synchronous timing mode and toggle timing mode separately, as described i n the following subsections. 3.9.4.1 asynchronous mode ac timing (onfi 1.0 compatible) asynchronous mode ac timings are provided as multiplications of the clock cycle and fixed delay. the maximum i/o speed of gpmi in a synchronous mode is about 50 mb/s . figure 20 through figure 23 depicts the relative timing betw een gpmi signals at the module level for different operations under asynchronous mode. table 47 describes the timing parameters (nf1Cnf17) that are shown in t he figures. 2'-))?28#attransmitter 2'-))?28$nnto 2'-))?28?#4, 2'-))?28#atreceiver 4skew4 28$6 28%22 4skew2 2'-))?28#sourceofdata 2'-))?28$nnto 2'-))?28?#4, 2'-))?28#atreceiver )nternaldelay 4setup4 4hold4 4setup2 4hold2 28$6 28%22
i.mx 8m dual / 8m quadlite / 8m quad applications processors da ta sheet for consumer pr oducts, rev. 0.1, 05/2018 48 nxp semiconductors electrical characteristics figure 20. command latc h cycle timi ng diagram figure 21. address latch cycle timing diagram figure 22. write data lat ch cycle timing diagram figure 23. read data latch cycle timing diagram (non-edo mode) }uuv .!.$?#,% .!.$?#%?" .!.$?7%?" .!.$?!,% .!.$?$!4!xx e&? e&? e& e& e&? e&? e& e&? e&e ??? e& e& e&? e&? e& e& e&? e& e&? .!.$?#,% .!.$?#%?" .!.$?7%?" .!.$?!,% eezd?? ??}e& e& e& e& e& e&? e& e&? .!.$?#,% .!.$?#%?" .!.$?7%?" .!.$?!,% .!.$?$!4!xx e&? e&? ?(?}ue& e&e e&? e& e& e&? e&? .!.$?#,% .!.$?#%?" .!.$?2%?" .!.$?2%!$9?" .!.$?$!4!xx
electrical characteristics i.mx 8m dual / 8m quadlite / 8m quad applications processors da ta sheet for consumer pr oducts, rev. 0.1, 05/2018 nxp semiconductors 49 figure 24. read data latch cyc le timing diagram (edo mode) table 47. asynchronous mode timing parameters 1 1 gpmis asynchronous mode output ti ming can be controlled by the modules internal registers hw_gpmi_timing0_address_setup, hw_gpmi_timing0_data_setup, and hw_gpmi_timing0_data_hold. this ac timing depends on th ese registers settings. in the table, as /ds/dh represents eac h of these settings. id parameter symbol timing t = gpmi clock cycle unit min. max. nf1 nand_cle setup time tcls (as + ds) t - 0.12 [see notes 2,3 ] 2 as minimum value can be 0, while ds/dh minimum value is 1. 3 t = gpmi clock period -0.075 ns (half of maxi mum p-p jitter). ns nf2 nand_cle hold time tclh dh t - 0.72 [see note 2 ]ns nf3 nand_ce0_b setup time tcs (as + ds + 1) t [see notes 3,2 ]ns nf4 nand_ce0_b hold time tch (dh+1) t - 1 [see note 2 ]ns nf5 nand_we_b pulse width twp ds t [see note 2 ]ns nf6 nand_ale setup time tals (as + ds) t - 0.49 [see notes 3,2 ]ns nf7 nand_ale hold time talh dh t - 0.42 [see note 2 ]ns nf8 data setup time tds ds t - 0.26 [see note 2 ]ns nf9 data hold time tdh dh t - 1.37 [see note 2 ]ns nf10 write cycle time twc (ds + dh) t [see note 2 ]ns nf11 nand_we_b hold time twh dh t [see note 2 ]ns nf12 ready to nand_re_b low trr 4 4 nf12 is guarantee d by the design. (as + 2) t [see 3,2 ]ns nf13 nand_re_b pulse width trp ds t [see note 2 ]ns nf14 read cycle time trc (ds + dh) t [see note 2 ]ns nf15 nand_re_b high hold time treh dh t [see note 2 ]ns nf16 data setup on read tdsr (ds t -0.67)/18.38 [see notes 5,6 ] 5 non-edo mode. 6 edo mode, gpmi clock 100 mhz (as=ds=dh=1, gpmi_ctl1 [rdn_delay] = 8, gpmi_ctl1 [half_period] = 0). ns nf17 data hold on read td hr 0.82/11.83 [see notes 5,6 ]ns ?(?}ue& e&e e&? e& e& e&? e&? .!.$?#,% .!.$?#%?" .!.$?2%?" .!.$?2%!$9?" eezd??
i.mx 8m dual / 8m quadlite / 8m quad applications processors da ta sheet for consumer pr oducts, rev. 0.1, 05/2018 50 nxp semiconductors electrical characteristics in edo mode ( figure 23 ), nf16/nf17 are diff erent from the defi nition in non-edo mode ( figure 22 ). they are called trea/trhoh (re # access time/re# high to output hold). the typical values for them are 16 ns (max for trea)/15 ns ( min for trhoh) at 50 mb/s edo m ode. in edo mode, gpmi samples nand_dataxx at the rising edge of delayed nand_re_b provided by an internal dpll. the delay value can be controlled by gpmi_ct rl1.rdn_delay (see the gpmi c hapter of the i.mx 8m dual / 8m quadlite / 8m quad applica tions processor reference manual [imx8mdqlqrm]). the typical value of this control register i s 0x8 at 50 mt/s edo mode. but if the board delay is big enough and cannot be ignored, the delay value should be made larger to compensate the board delay. 3.9.4.2 source synchronous mode ac timing (onfi 2.x compatible) figure 25 to figure 27 show the write and read tim ing of source synchronous mode. figure 25. source synchronous mode command and address timing di agram 1) 1) 1) 1) 1) 1) 1) 1) 1) 1) 1) 1) 1) &0' $'' .!.$?#%?" 1$1'b&/( 1$1'b$/( 1$1'b:(5(b% 1$1'b&/. 1$1'b'46 1$1'b'46 2xwsxwhqdeoh 1$1'b'$7$>@ 1$1'b'$7$>@ 2xwsxwhqdeoh
electrical characteristics i.mx 8m dual / 8m quadlite / 8m quad applications processors da ta sheet for consumer pr oducts, rev. 0.1, 05/2018 nxp semiconductors 51 figure 26. source synchronous mo de data write timing diagram figure 27. source synchronous mode data read timing diagram 1) 1) 1) 1) 1) 1) 1) 1) 1) 1) 1) 1) 1) 1) 1) 1) 1) .!.$?#%?" .!.$?#,% .!.$?!,% 1$1'b:(5(b% .!.$?#,+ .!.$?$13 .!.$?$13 2xwsxwhqdeoh .!.$?$1;= .!.$?$1;= 2xwsxwhqdeoh 1) 1) 1) 1) 1) 1) 1) 1) 1) 1) 1) 1) 1) .!.$?#%?" .!.$?#,% 1$1'b$/( .!.$?7%2% .!.$?#,+ .!.$?$13 .!.$?$13 /utputenable .!.$?$!4!;= .!.$?$!4!;= /utputenable 1)
i.mx 8m dual / 8m quadlite / 8m quad applications processors da ta sheet for consumer pr oducts, rev. 0.1, 05/2018 52 nxp semiconductors electrical characteristics figure 28. nand_dqs/nand_dq read valid window for ddr source synchronous mode, figure 28 shows the timing diagram of nand_dqs/nand_dataxx read valid window. the typical value of td qsq is 0.85 ns (max) and 1 ns (max) for tqhs at 200 mb/s. gpmi will sample nand_data[7:0] at b oth rising and falling edge of an delayed nand_dqs signal, whi ch can be provided by an internal d pll. the delay value can be controlled by gpmi regi ster gpmi_read_ddr_dl l_ctrl.slv_dly_targ et (see the gpmi chapter of the i.mx 8m dual / 8m quadlite / 8m quad applications proces sor reference manual [imx8mdqlqrm]). generally, the typical delay value of this regi ster is equal to 0x7 which means 1/4 clock cycle delay exp ected. but if the board delay is big enoug h and cannot be ignored, the delay value should be made larger to com pensate the board delay. table 48. source synchronous mode timing parameters 1 1 gpmis source synchronous mode out put timing can be controlled by the modules internal regis ters gpmi_timing2_ce_delay, gpmi_timing_preamble_delay, gpmi _timing2_post_delay. this ac ti ming depends on these regi sters settings. in the table, ce_delay/pre_delay/post_delay represents each of these s ettings. id parameter symbol timing t = gpmi clock cycle unit min. max. nf18 nand_ce0_b acces s time tce ce_delay t - 0.79 [see note 2 ] 2 t = tck(gpmi clock period) C0.075 ns (half of max imum p-p jitte r). ns nf19 nand_ce0_b hold time tch 0.5 tck - 0.63 [see note 2 ]ns nf20 command/address nand_dataxx setup time tcas 0.5 tck - 0.05 ns nf21 command/address nand_ dataxx hold time tcah 0.5 tck - 1.23 ns nf22 clock period tck ns nf23 preamble delay tpre pre_delay t - 0.29 [see note 2 ]ns nf24 postamble delay tpost post_delay t - 0.78 [see note 2 ]ns nf25 nand_cle and nand_ale setup time tcals 0.5 tck - 0.86 ns nf26 nand_cle and nand_ale hold time tcalh 0.5 tck - 0.37 ns nf27 nand_clk to first nand_dqs lat ching transition tdqss t - 0.41 [see note 2 ]ns nf28 data write setup 0.25 tck - 0.35 nf29 data write hold 0.25 tck - 0.85 nf30 nand_dqs/nand_dq rea d setup skew 2.06 nf31 nand_dqs/nand_dq read hold skew 1.95 ? ? .!.$?$13 .!.$?$!4!;= e&? e&? e&? e&?
electrical characteristics i.mx 8m dual / 8m quadlite / 8m quad applications processors da ta sheet for consumer pr oducts, rev. 0.1, 05/2018 nxp semiconductors 53 3.9.4.3 onfi nv-ddr2 mod e (onfi 3.2 compatible) 3.9.4.3.1 command and address timing onfi 3.2 mode command and address timing is the same as onfi 1. 0 compatible async mode ac timing. see section 3.9.4.1, asynchronous mode ac timing (onfi 1.0 compatib le) , for details. 3.9.4.3.2 read and write timing onfi 3.2 mode read and write timing is the same as toggle mode ac timing. see section 3.9.4.4, toggle mode ac timing , for details. 3.9.4.4 toggle mode ac timing 3.9.4.4.1 command and address timing note toggle mode command and address timing is the same as onfi 1.0 compatible asynchronous mode ac timing. see section 3.9.4.1, asynchronous mode ac timi ng (onfi 1.0 compatible), for details. 3.9.4.4.2 read and write timing figure 29. toggle mode data write timing
i.mx 8m dual / 8m quadlite / 8m quad applications processors da ta sheet for consumer pr oducts, rev. 0.1, 05/2018 54 nxp semiconductors electrical characteristics figure 30. toggle mode data read timing table 49. toggle mode timing parameters 1 id parameter symbol timing t = gpmi clock cycle unit min. max. nf1 nand_cle setup time tcls (as + ds) t - 0.12 [see note 2 s ,3 ] nf2 nand_cle hold time tclh dh t - 0.72 [see note 2 ] nf3 nand_ce0_b setup time tcs (as + ds) t - 0.58 [see notes ,2 ] nf4 nand_ce0_b hold time tch dh t - 1 [see note 2 ] nf5 nand_we_b pulse width twp ds t [see note 2 ] nf6 nand_ale setup time tals (as + ds) t - 0.49 [see notes ,2 ] nf7 nand_ale hold time talh dh t - 0.42 [see note 2 ] nf8 command/address nand_ dataxx setup time tcas ds t - 0.26 [see note 2 ] nf9 command/address nand_dataxx hold time tcah dh t - 1.37 [see note 2 ] nf18 nand_cex_b access time tce ce_delay t [see notes 4,2 ]ns nf22 clock period tck ns nf23 preamble delay tpre pre_delay t [see notes 5,2 ]ns dev?clk .!.$?#%x?" .!.$?#,% .!.$?!,% .!.$?7%?" .!.$?2%?" .!.$?$13 .!.$?$!4!;= .& t#+ t#+ .& t#+ t#+ .& t#+
electrical characteristics i.mx 8m dual / 8m quadlite / 8m quad applications processors da ta sheet for consumer pr oducts, rev. 0.1, 05/2018 nxp semiconductors 55 for ddr toggle mode, figure 28 shows the timing diagram of nand_dqs/nand_dataxx read valid window. the typical value of tdqsq is 1.4 ns (max) and 1.4 ns ( max) for tqhs at 133 mb/s. gpmi samples nand_data[7:0 ] at both the ri sing and falli ng edges of a delayed nand_dqs signal, which is provided by an internal dpll. t he delay value of this regist er can be controlled by t he gpmi register gpmi_read_ddr_dll_ctrl.slv_dly_t arget (see the gpmi chapter of the i.mx 8m dual / 8m quadlite / 8m quad applications processor reference manual [imx8mdqlqrm]). g enerally, the typical delay value is equal to 0x7, which means a 1/4 clock cy cle delay is expected. but if the board delay is big enough and cannot be ignored, the delay value should be made larger to compensate the board delay. 3.9.5 hdmi 2.0 tx module timing parameters see the following specifications: ? hdmi 2.0a specification (hdmi.org) ? displayport 1.3 standard (vesa.org) dp supports 1.6 ghz (rbr), 2.7 ghz (hbr), and 5.4 ghz (hbr2) r ates. those rates are managed in api (host). rbr supports 1080p60 (rgb 8b), hbr supports 4kp30 (rgb 8b) and hbr2 supports 4kp60 (rgb 8b). see bandwidth details below. effective bandwidth per rate with 4 lanes: rbr: 1.62 x 4 x 8 / 10 = 5.184 gbps hbr: 2.7 x 4 x 8 / 10 = 8.64 gbps nf24 postamble delay tpost post_delay t +0.43 [see note 2 ] ns nf28 data wri te setup tds 6 0.25 tck - 0.32 ns nf29 data write hold tdh 6 0.25 tck - 0.79 ns nf30 nand_dqs/nand_dq read setup skew tdqsq 7 3.18ns nf31 nand_dqs/nand_dq read hold skew tqhs 7 3.27ns 1 the gpmi toggle mode output timing can be c ontrolled by the mod ules internal registers hw_ gpmi_timing0_address_setup, hw_gpmi_timing0_data_setup, and hw_gpmi_timing0_data_hold. this ac timing depends on these registers settings. in the table, as/ds/dh represents each of these settings. 2 as minimum value can be 0, while ds/dh minimum value is 1. 3 t = tck (gpmi cl ock period) -0.075 ns (half of maximum p-p jitte r). 4 ce_delay represents hw_gpmi_timi ng2[ce_delay]. nf18 is guarante ed by the design. read/writ e operation is started with enough time of ale/cle assertion to low level. 5 pre_delay+1 (as+ds) 6 shown in figure 29 . 7 shown in figure 30 . table 49. toggle mode timing parameters 1 (continued) id parameter symbol timing t = gpmi clock cycle unit min. max.
i.mx 8m dual / 8m quadlite / 8m quad applications processors da ta sheet for consumer pr oducts, rev. 0.1, 05/2018 56 nxp semiconductors electrical characteristics hbr2: 1.62 x4 x 8 / 10 = 17.28 gbps bandwidth required per resolution (cea-861-f): 1920 x 1080 (24 b/px) 60 fps: 3.56 gbps 3840 x 2160 (24 b/px) 30 fps: 7.13 gbps 3840 x 2160 (24 b/px) 30 fps: 14.26 gbps ? embedded displayport 1.4 standard (vesa.org) edp link rates: r216 (2.16 gbps), r243 (2.43 gbps), r324 (3.24 gbps), and r432 (4.32 gbps) fast link training is also supported ddc link requires external pull- up resistors to be connected to a 5 v supply. the following table provides the range for those pull-ups. 3.9.6 i 2 c bus characteristics the inter-integrated circuit ( i2c) provides functionality of a standard i2c master and slave. the i2c is designed to be compatible with t he i2c bus specification, versi on 2.1, by philips semic onductor (now nxp semiconductors). 3.9.7 mipi d-phy timing parameters this section describes mipi d-p hy electrical specifications. 3.9.7.1 mipi hs-tx specifications table 50. pull-up resistors for ddc link ball name min typ max unit hdmi_tx0_ddc_scl 1.5 2 k hdmi_tx0_ddc_sda 1.5 2 k table 51. mipi high-speed tra nsmitter dc specifications symbol parameter min typ max unit v cmtx 1 1 value when driving into load impedance anywhere in the z id range. high speed transmit static c ommon mode voltage 150 200 250 mv | v cmtx | (1,0) v cmtx mismatch when output is differential-1 or differential-0 3 mv |v od | 1 high speed transmit diffe rential voltage 140 200 270 mv | v od |v od mismatch when output is differential-1 or differential-0 12 mv v ohhs 1 high speed output high voltage 360 mv z os single ended output impedance 40 50 62.5 z os single ended output imp edance mismatch 10 %
electrical characteristics i.mx 8m dual / 8m quadlite / 8m quad applications processors da ta sheet for consumer pr oducts, rev. 0.1, 05/2018 nxp semiconductors 57 3.9.7.2 mipi lp-tx specifications table 52. mipi high-speed tra nsmitter ac specifications symbol parameter min typ max unit v cmtx(hf) common-level variati ons above 450 mhz 8 mv rms v cmtx(lf) common-level variation be tween 50-450 mhz 10 mv peak t r and t f 1 1 ui is the long-term ave rage unit interval. rise time and fall time (20% to 80%) 160 0.3 ui ps table 53. mipi low-power tr ansmitter dc sp ecifications symbol parameter min typ max unit v oh 1 1 this specification ca n only be met w hen limiting the core suppl y variation from 1.1 v to 1.3 v. thevenin output high level 1.1 1.2 1.3 v v ol thevenin output low level -50 50 mv z olp 2 2 although there is no spec ified maximum for z olp , the lp transmitter output impedance ensures the t rlp /t flp specificati on is met. output impedance of low power transmitter 110 table 54. mipi low-power tr ansmitter ac sp ecifications symbol parameter min typ max unit t rlp /t flp 1 1 c load includes the low equivalent tra nsmission line capacitance of t x and rx are assumed t o always be < 10 pf. the distributed line capacitance can be up to 50 pf for a tra nsmission line with 2 n s delay. 15% to 85% rise time and fall time 25 ns t reot 1,2,3 2 the rise-time of t reot starts from the hs common-level at the moment when the differe ntial amplitude drops below 70 mv, due to stopping of the dif ferential drive. 3 with an additional load capacit ance ccm between 0 to 60 pf on t he termination center, tap at rx side of the lane. 30% to 85% rise time and fall time 35 ns t lp-pulse-tx 4 4 this parameter value can be lower than tlpx, due to differences in rise vs. fall signal slopes, trip levels, and mismatches be tween dp and dn lp transmitters. any lp e xclusive-or puls e observed duri ng hs eot (transition from hs level to lp-11) is glitch behavio r as described in low-pow er receiver section. pulse width of the lp exclusive- or clock: first lp exclusive-or clock pulse after stop state or l ast pulse before stop state 40 ns pulse width of the lp exclusive- or clock: all other pulses 20 n s t lp-per-tx period of the lp exclusive-or clock 90 ns v/ t sr 1,5,6,7 slew rate @ c load = 0 pf 30 500 mv/ns slew rate @ c load = 5 pf 30 200 mv/ns slew rate @ c load = 20 pf 30 150 mv/ns slew rate @ c load = 70 pf 30 100 mv/ns c load load capacitance 0 70 pf
i.mx 8m dual / 8m quadlite / 8m quad applications processors da ta sheet for consumer pr oducts, rev. 0.1, 05/2018 58 nxp semiconductors electrical characteristics 3.9.7.3 mipi lp-rx specifications 3.9.7.4 mipi lp-cd specifications 3.9.7.5 mipi dc specifications 5 when the output voltage is betw een 15% and 85% of the fully set tled lp signal levels. 6 measured as average across any 50 mv segment of the output sign al transition. 7 this value represents a corner point in a piecew ise linear curv e. table 55. mipi low power receiver dc specifications symbol parameter min typ max unit v ih logic 1 input voltage 880 1.3 mv v il logic 0 input voltage, not in ulp state 550 mv v il-ulps logic 0 input voltage , ulp state 300 mv v hyst input hysteresis 25 mv table 56. mipi low power receiver ac specifications symbol parameter min typ max unit e spike 1,2 1 time-voltage integra tion of a spike above v il when in lp-0 state or below v ih when in lp-1 state. 2 an impulse below thi s value will not change the receiver state. input pulse rejection 300 v.ps t min-rx 3 3 an input pulse greater than this value sha ll toggle the output. minimum pulse width response 20 0 0 ns v int peak interference amplitude 200 mv f int interference frequency 450 mhz table 57. mipi contention d etector dc specifications symbol parameter min typ max unit v ihcd logic 1 contention threshold 450 mv v ilcd logic 0 contention threshold 200 mv table 58. mipi input charac teristics dc specifications symbol parameter min typ max unit v pin pad signal voltage range -50 1350 mv i leak 1 pin leakage current -30 30 a v gndsh ground shift -50 50 mv
electrical characteristics i.mx 8m dual / 8m quadlite / 8m quad applications processors da ta sheet for consumer pr oducts, rev. 0.1, 05/2018 nxp semiconductors 59 3.9.8 pcie phy parameters the pcie interface is designed to be compatible with pcie speci fication gen2 x1 lane and supports the pci express 1.1/2.0 standard. 3.9.8.1 pciex_resref reference resistor connection the impedance calibration proce ss requires connection of refere nce resistor 200 . 1% precision resistor on pciex_resref pads to ground. it is used for termination impe dance calibration. 3.9.9 pulse width modulator (pwm) timing parameters this section describes the electr ical information of the pwm. t he pwm can be programmed to select one of three clock signals as its source frequency. the selected cl ock signal is passed through a prescaler before being input to the counter. the output is available at the puls e-width modulator out put (pwmo) external pin. figure 31 depicts the timing of the pwm, and table 59 lists the pwm timing parameters. figure 31. pwm timing 3.9.10 quad spi (qspi) timing parameters this section describes the elec trical information for qspi. v pin(absmax) 2 maximum pin voltage level -0.15 1.45 v t vpin(absmax) 3 maximum transient time above v pin(max) or below v pin(min) 20ns 1 when the pad voltage is within t he signal voltage range between v gndsh(min) to v oh + v gndsh(max) and the lane module is in lp receive mode. 2 this value includes ground shift. 3 the voltage overshoot and undershoot beyond the v pin is only allowed during a single 20 ns window af ter any lp-0 to lp-1 transition or vice versa. for all other situations it must stay within the v pin range. table 59. pwm output timing parameters id parameter min max unit pwm module clock frequency 0 ipg_clk (66 mhz) mhz p1 pwm output pulse width high 15 ns p2 pwm output pulse width low 15 ns table 58. mipi input characterist ics dc specifications (continue d) 07-n?/54 0 0
i.mx 8m dual / 8m quadlite / 8m quad applications processors da ta sheet for consumer pr oducts, rev. 0.1, 05/2018 60 nxp semiconductors electrical characteristics measurement is with a load of 35 pf on sck and sio pins and an input slew rate of 1 v/ns. 3.9.10.1 sdr mode figure 32. quadspi input/read tim ing (sdr mode with internal sam pling) figure 33. quadspi input/read tim ing (sdr mode with loopback dqs sampling) note ? for internal sampling, the timi ng values assume using sample p oint 0, that is quadspix_smpr[sdrsmp] = 0. table 60. quadspi input timing (sdr mode with internal sampling) symbol parameter value unit min max t is setup time for inc oming data 8.67 ns t ih hold time requi rement for inc oming data 0 ns table 61. quadspi input /read timing (sdr mode with loopback dqs sampling) symbol parameter value unit min max t is setup time for i ncoming data 2 ns t ih hold time requirement f or incoming data 1 ns 7 ,6 7 ,+ 7 ,6 7 ,+ 463,[b6&/. 463,[b'$7$>@ 7 ,6 7 ,6 7 ,+ 7 ,+ 463,[b6&/. 463,[b'$7$>@ 463,[b'46
electrical characteristics i.mx 8m dual / 8m quadlite / 8m quad applications processors da ta sheet for consumer pr oducts, rev. 0.1, 05/2018 nxp semiconductors 61 ? for loopback dqs sampling, the da ta strobe is output to the dq s pad together with the serial clock. the data strobe is looped back from dqs pad and used to sample input data. figure 34. quadspi output/write timing (sdr mode) note t css and t csh are configured by the quadspix_f lshcr register; the default value of 3 is shown on the timing. see the i.mx 8m dual / 8m quadlite / 8m quad applications pr ocessor reference manual (imx8mdqlqrm) for more details. table 62. quadspi output/write timing (sdr mode) symbol parameter value unit min max t dvo output data valid time 2 ns t dho output data hold time -0.5 ns t ck sck clock period 10 ns t css chip select output setup time 3 ns t csh chip select output hold time 3 ns 7 &66 7 &. 7 &6+ 7 '92 7 '+2 7 '92 7 '+2 463,[b6&/. 463,[b&6 463,[b6,2
i.mx 8m dual / 8m quadlite / 8m quad applications processors da ta sheet for consumer pr oducts, rev. 0.1, 05/2018 62 nxp semiconductors electrical characteristics 3.9.10.2 ddr mode figure 35. quadspi input/read timing (ddr mode with internal sam pling) figure 36. quadspi input/read ti ming (ddr mode with loopback dqs sampling) note ? for internal sampling, the timi ng values assume using sample p oint 0, that is quadspix_smpr[sdrsmp] = 0. table 63. quadspi input /read timing (ddr mode with internal samp ling) symbol parameter value unit min max t is setup time for inc oming data 8.67 ns t ih hold time requirement f or incoming data 0 ns table 64. quadspi input/read timin g (ddr mode with loopback dqs sampling) symbol parameter value unit min max t is setup time for i ncoming data 2 ns t ih hold time requirement f or incoming data 1 ns 7 ,6 7 ,+ 7 ,6 7 ,+ 463,[b6&/. 463,[b'$7$>@ 7 ,6 7 ,+ 7 ,6 7 ,+ 463,[b6&/. 463,[b'$7$>@ 463,[b'46
electrical characteristics i.mx 8m dual / 8m quadlite / 8m quad applications processors da ta sheet for consumer pr oducts, rev. 0.1, 05/2018 nxp semiconductors 63 ? for loopback dqs sampling, the da ta strobe is output to the dq s pad together with the serial clock. the data strobe is looped back from dqs pad and used to sample input data. figure 37. quadspi output/write timing (ddr mode) note t css and t csh are configured by the quadspix_fls hcr register; the default va lue of 3 is shown on the timing. see the i.mx 8m dual / 8m quadlite / 8m quad applications processor reference manual (imx8mdqlqrm) for more details. 3.9.11 sai/i2s switch ing specifications this section provides the ac timi ngs for the sai in master (clo cks driven) and slave (clocks input) modes. all timings are given for non inve rted serial cl ock polarity (s ai_tcr[tsckp] = 0, sai_rcr[rsckp] = 0) and non inverted frame sync ( sai_tcr[tfsi] = 0, sai_rcr[rf si] = 0). if the polarity of the clock and/or the frame sync have been i nverted, all the timings remai n valid by inverting the clock signal (sai_bclk) and/or the frame sync (sai_fs) shown in the figures below. table 65. quadspi output/write timing (ddr mode) symbol parameter value unit min max t dvo output data valid time (0.25 x t sclk ) + 2 ns t dho output data hold time (0.25 x t sclk ) - 0.5 ns t ck sck clock period 20 ns t css chip select output set up time 3 sck cycle(s) t csh chip select output hold time 3 ns table 66. master mode sai timing num characteristic min max unit s1 sai_mclk cycle time 20 ns s2 sai_mclk pulse width high/low 40% 60% mclk period s3 sai_bclk cycle time 40 ns 7 &66 7 &. 7 '92 7 '+2 7 '92 7 '+2 7 &6+ 463,[b6&/. 463,[b&6 463,[b6,2
i.mx 8m dual / 8m quadlite / 8m quad applications processors da ta sheet for consumer pr oducts, rev. 0.1, 05/2018 64 nxp semiconductors electrical characteristics figure 38. sai timingmaster modes s4 sai_bclk pulse width hig h/low 40% 60% bclk period s5 sai_bclk to sai_fs output valid 15 ns s6 sai_bclk to sai_fs output invalid 0 ns s7 sai_bclk to sai_txd valid 15 ns s8 sai_bclk to sai_txd invalid 0 ns s9 sai_rxd/sai_fs input se tup before sai_bclk 15 ns s10 sai_rxd/sai_fs inpu t hold after sai_bclk 0 ns table 67. slave mode sai timing num characteristic min max unit s11 sai_bclk cycle time (input) 40 ns s12 sai_bclk pulse width high/ low (input) 40% 60% bclk period s13 sai_fs input setup before sai_bclk 10 ns s14 sai_fa input ho ld after sai_bclk 2 ns s15 sai_bclk to sai_txd /sai_fs output valid 20 ns s16 sai_bclk to sai_txd/s ai_fs output invalid 0 ns s17 sai_rxd setup before sai_bclk 10 ns s18 sai_rxd hold after sai_bclk 2 ns table 66. master mode sai timing (continued) num characteristic min max unit
electrical characteristics i.mx 8m dual / 8m quadlite / 8m quad applications processors da ta sheet for consumer pr oducts, rev. 0.1, 05/2018 nxp semiconductors 65 figure 39. sai timing slave modes 3.9.12 spdif timing parameters the sony/philips digital interc onnect format (spdif) data is se nt using the bi-phase marking code. when encoding, the spdif data signal is modulated by a clock that is twice the bit rate of the data signal. table 68 and figure 40 and figure 41 show spdif timing parameters f or the sony/philips digital interconnect format (spdif), inc luding the timing of the modula ting rx clock (spdif_sr_clk) for spdif in rx mode and the timing of the modulating tx clock (spd if_st_clk) for spdif in tx mode. table 68. spdif t iming parameters parameter symbol timing parameter range unit min max spdif_in skew: asynchronous i nputs, no specs apply 0.7 ns spdif_out output (load = 50 pf) ? skew ? transition rising ? transition falling 1.5 24.2 31.3 ns spdif_out output (load = 30 pf) ? skew ? transition rising ? transition falling 1.5 13.6 18.0 ns modulating rx clock (spdif_s r_clk) period srckp 40.0 ns spdif_sr_clk high period srckph 16.0 ns spdif_sr_clk low period srckpl 16.0 ns modulating tx clock (spdif_ st_clk) period stclkp 40.0 ns spdif_st_clk high period stclkph 16.0 ns spdif_st_clk low period stclkpl 16.0 ns
i.mx 8m dual / 8m quadlite / 8m quad applications processors da ta sheet for consumer pr oducts, rev. 0.1, 05/2018 66 nxp semiconductors electrical characteristics figure 40. spdif_sr_clk timing diagram figure 41. spdif_st _clk timing diagram 3.9.13 uart i/o configurati on and timing parameters 3.9.13.1 uart rs-232 i/o configuration in different modes the uart interfaces of the i.mx 8m dual / 8m quadlite / 8m quad processors can serve both as dte or dce device. this can be confi gured by the dcedte control bit (default 0dce mode). table 69 shows the uart i/o configurat ion based on the enabled mode. 3.9.13.2 uart rs-232 serial mode timing this section describes the elec trical information of the uart m odule in the rs-232 mode. table 69. uart i/o configuration vs. mode port dte mode dce mode direction description direction description uartx_rts_b output uartx_rts_b fro m dte to dce input uartx_rts_b fr om dte to dce uartx_cts_b input uartx_cts_b from dce to dte output uartx_cts_b fr om dce to dte uartx_tx_ data input serial data from dce to dte output serial data from dce to dte uartx_rx _data output serial data f rom dte to dce input serial data from dte to dce spdif_sr_clk (output) v m v m srckp srckph srckpl spdif_st_clk (input) v m v m stclkp stclkph stclkpl
electrical characteristics i.mx 8m dual / 8m quadlite / 8m quad applications processors da ta sheet for consumer pr oducts, rev. 0.1, 05/2018 nxp semiconductors 67 3.9.13.2.1 uart transmitter figure 42 depicts the transmit timing of uart in t he rs-232 serial mode, with 8 data bit/1 stop bit format. table 70 lists the uart rs-232 serial m ode transmit timing characterist ics. figure 42. uart rs-232 serial mode transmit timing diagram 3.9.13.2.2 uart receiver figure 43 depicts the rs-232 serial m ode receive timing with 8 data bit/ 1 stop bit format. table 71 lists serial mode receive ti ming characteristics. figure 43. uart rs-232 serial mode receive timing diagram table 70. rs-232 serial mode transmit timing parameters id parameter symbol min max unit ua1 transmit bit time t tbit 1/f baud_rate 1 - t ref_clk 2 1 f baud_rate : baud rate frequency. the maximum baud rate the uart can suppo rt is ( ipg_perclk frequency)/16. 2 t ref_clk : the period of uar t reference clock ref_clk ( ipg_perclk after rfdiv divider). 1/f baud_rate + t ref_clk table 71. rs-232 serial mode receive timing parameters id parameter symbol min max unit ua2 receive bit time 1 1 the uart receiver can tolerate 1/(16 x f baud_rate ) tolerance in each bit. but acc umulation tolerance in one fram e must not exceed 3/(16 x f baud_rate ). t rbit 1/f baud_rate 2 - 1/(16 x f baud_rate ) 2 f baud_rate : baud rate frequency. the maximu m baud rate the uart can suppo rt is ( ipg_perclk frequency)/16. 1/f baud_rate + 1/(16 x f baud_rate ) start bit bit 1 bit 2 bit 0 bit 4 bit 5 bit 6 bit 7 uartx_tx_data (output) bit 3 stop bit next start bit possible parity bit par bit ua1 ua1 ua1 ua1 bit 1 bit 2 bit 0 bit 4 bit 5 bit 6 bit 7 uartx_rx_data (output) bit 3 start bit stop bit next start bit possible parity bit par bit ua2 ua2 ua2 ua2
i.mx 8m dual / 8m quadlite / 8m quad applications processors da ta sheet for consumer pr oducts, rev. 0.1, 05/2018 68 nxp semiconductors electrical characteristics 3.9.14 usb phy parameters this section describes the usb-otg phy parameters. the usb phy meets the electrical compliance requirements define d in the universal serial bus revision 3.0 otg, usb host with the amendments below (on-the-go and embe dded host supplement to the usb revision 3.0 specification is no t applicable to host port): ? usb engineering change notice title: 5v short circuit withstand requirement change applies to: universal serial bus specification, revision 2.0 ? errata for usb revisi on 2.0 april 27, 2000 as of 12/7/2000 ? usb engineering change notice title: pull-up/pull-down resistors applies to: universal serial bus specification, revision 2.0 ? usb engineering change notice title: suspend cur rent limit changes applies to: universal serial bus specification, revision 2.0 ? usb engineering change notice title: usb 2.0 phase locked sofs applies to: universal serial bus specification, revision 2.0 ? on-the-go and embedded host s upplement to the usb revision 2.0 specification revision 2.0, version 1.1a, july 27, 2010 ? battery charging specificat ion (available from usb-if) revision 1.2, december 7, 2010 3.9.14.1 usb_otg*_rext refere nce resistor connection the bias generation and impedance calibration process for the u sb otg phys requires connection of reference resistors 200 1% precision on each of usb_otg1_r ext and usb_otg2_rext pads t o ground. 3.9.14.2 usb_otg_chd_b us b battery charger detection external pu llup resistor connection the usage and external resistor connection for the usb_otg_chd_ b pin are described in table 5 , and section 3.7.3, usb battery charg er detection driver impedance . 3.9.15 usb 2.0 phy parameters usb 2.0 phy parameters are com patible with usb 3.0 phy. see section 3.9.16, usb 3.0 phy parameters for more detailed information.
electrical characteristics i.mx 8m dual / 8m quadlite / 8m quad applications processors da ta sheet for consumer pr oducts, rev. 0.1, 05/2018 nxp semiconductors 69 3.9.16 usb 3.0 phy parameters this section describes the el ectrical infor mation about usb 3.0 phy. table 72 shows the usb 3.0 phy junction temperature. table 73 shows the usb 3.0 phy power di ssipation of superspeed 5-gbps o peration. table 74 shows the usb 3.0 phy power di ssipation: hs/fs/ls operation. table 75 shows the worst-case maximum current. table 76 shows the usb po wer pin supplies. table 72. usb 3.0 phy junction temperature min max -40 c 125 c table 73. usb 3.0 phy power dissi pation: superspeed 5-gbps opera tion (unit: for current is ma, for power is mw) mode conditions current from usb1/2_vp current from usb1/2_vptx current from usb1/2_vph total current total power u0 tt/wc 25.700/35.700 15.000/21.200 14.000/20.300 54.700/77.200 82.800 /130.000 power-down tt/wc 0.318/2.550 0.012/0.184 0.012/0. 030 0.34/2.764 0.337/2.816 table 74. usb 3.0 phy power dissipa tion: hs/fs/ls operations (un it: for current is m a, for power is mw) mode conditions current from usb1/2_dvdd current from usb1/2_vdd33 total current total power hs tx tt/wc 4.800/9.200 24.000/24.400 28.800/33.600 83.500/97.700 fs tx tt/wc 2.800/6.800 22.100/24.500 24. 900/31.200 75.400/95.500 ls tx tt/wc 3.500/7.700 19.300/20.400 22. 800/28.100 66.900/81.700 power-down tt/wc 0.048/3.690 0.065/0.146 0.112/3.386 0.257/4.182 suspend tt/wc 0.047/3.690 0.066/0.154 0.113/3.844 0.261/4.213 battery charging tt/wc 0.122/3.760 6.350/5.780 6. 472/9.540 21.065/24.704 table 75. worst-cas e maximum current usb1/2_vph usb1/2_vp usb1/2_vp tx usb1/2_vdd33 usb1/2_dvdd unit 20.3 35.7 21.2 24.5 9.2 ma table 76. usb power pin supplies pin name description value usb1/2_vdd phy analog and digita l high-speed supply 0.9 v (+22.2%, -7%) usb1/2_vp phy analog and digita l superspeed supply 0 .9 v (+22.2%, -7%)
i.mx 8m dual / 8m quadlite / 8m quad applications processors da ta sheet for consumer pr oducts, rev. 0.1, 05/2018 70 nxp semiconductors electrical characteristics table 77 shows the external component values. table 78 shows the minimum esd pr otection target levels. table 79 shows the supply impedance requirements. usb1/2_vptx phy transmit supply 0.9 v (+22.2%, -7%) usb1/2_vdd33 high supply for high-speed op eration io 3.3 v (+10%, -7%) usb1/2_vph high supply for superspeed operation io 3.3 v (+10%, -7%) table 77. external component values component pin name value external resistor (resref) usb1_resref/usb2_resref 200 (1%) table 78. minimum esd pro tection target levels esd category minimum prote ction level jedec class human body model (hbm) (js-001-2014) 2 kv 2 charged device model (cdm) (jesd22-c101f) 6 a peak discharge current c2/c1 (500 v/ 250 v) 1 1 support for either 500 v or 250 v cdm target level is dependent on maximum discharg e current generated in final soc/package implementation. machine model (mm) (jesd22_a115c) 100 v n/a table 79. supply impedance requirements l gd + l vp (nh) l vssa <#> + l dvdd (nh) l gd + l vptx <#> (nh) l vssa <#> + l vdd33 <#> (nh) l gd + l vph (nh) < 2.4 < 2.4 < 2.4 < 2.8 < 2.8 table 76. usb power pin supplies (continued) pin name description value
boot mode configuration i.mx 8m dual / 8m quadlite / 8m quad applications processors da ta sheet for consumer pr oducts, rev. 0.1, 05/2018 nxp semiconductors 71 4 boot mode configuration this section provides informati on on boot mode configuration pi ns allocation and boot devices interfaces allocation. 4.1 boot mode configuration pins table 80 provides boot options, functiona lity, fuse values, and associa ted pins. several input pins are also sampled at reset and can be used to override fuse values, depen ding on the value of bt_fuse_sel fuse. the boot option pins are in effect when bt_fuse_sel fuse is 0 (cleared, which is the case for an unblown fuse). for detailed boot mode options configured by the boot mode pins, see the system boot, fusemap, and efuse chapter in the i.mx 8m dual / 8m quadlite / 8m quad applications processor reference manual (imx8mdqlqrm). table 80. fuses and associated pins used for boot pin direction at reset efuse name state during reset (por_b asserted) state after reset (por_b deasserted) details boot_mode0 input n/a input with 95 k pull down input with 95 k pull down boot mode selection boot_mode1 input n/a input with 95 k pull down input with 95 k pull down boot mode selection sai1_rxd0 input boot_cfg[0] input with 95 k pull do wn input with 95 k pull down boot options pin value overrides fuse settings for bt_fuse_sel = 0. signal configuration as fuse override input at power up. these are special i/o lines that control the boot configuration during product development. in production, the boot configuration can be controlled by fuses. sai1_rxd1 input boot_cfg[1] input with 95 k pull do wn input with 95 k pull down sai1_rxd2 input boot_cfg[2] input with 95 k pull do wn input with 95 k pull down sai1_rxd3 input boot_cfg[3] input with 95 k pull do wn input with 95 k pull down sai1_rxd4 input boot_cfg[4] input with 95 k pull do wn input with 95 k pull down sai1_rxd5 input boot_cfg[5] input with 95 k pull do wn input with 95 k pull down sai1_rxd6 input boot_cfg[6] input with 95 k pull do wn input with 95 k pull down sai1_rxd7 input boot_cfg[7] input with 95 k pull do wn input with 95 k pull down sai1_txd0 input boot_cfg[8] input with 95 k pull do wn input with 95 k pull down sai1_txd1 input boot_cfg[9] input with 95 k pull do wn input with 95 k pull down sai1_txd2 input boot_cfg[10] inpu t with 95 k pull do wn input with 9 5 k pull down sai1_txd3 input boot_cfg[11] inpu t with 95 k pull do wn input with 9 5 k pull down sai1_txd4 input boot_cfg[12] inpu t with 95 k pull do wn input with 9 5 k pull down sai1_txd5 input boot_cfg[13] inpu t with 95 k pull do wn input with 9 5 k pull down sai1_txd6 input boot_cfg[14] inpu t with 95 k pull do wn input with 9 5 k pull down sai1_txd7 input boot_cfg[15] inpu t with 95 k pull do wn input with 9 5 k pull down
i.mx 8m dual / 8m quadlite / 8m quad applications processors da ta sheet for consumer pr oducts, rev. 0.1, 05/2018 72 nxp semiconductors boot mode configuration 4.2 boot device interface allocation table 81 lists the interfaces that can be used by the boot process in a ccordance with the specific boot mode configuration. the table a lso describes the interfaces sp ecific modes and iomuxc allocation, which are configured dur ing boot when appropriate. table 81. interface allocation during boot interface ip instance alloca ted pads during boot comment nand flash gpmi nand_ale, nand_ce0_b, nand_cle, nand_data00, nand_data01, nand_data02, nand_data03, nand_data04, nand_data05, nand_data06, nand_data07, nand_dqs, nand_re_b, nand_ready_b, nand_we_b, nand_wp_b 8-bit, only cs 0 is supported. sd/mmc usdhc-1 gpio1_io03, g pio1_io06, gpio1_io07, sd1_reset_b, sd1_clk, sd1_cmd, sd1_strobe, sd1_data0, sd1_data1, sd1_data2, sd1_data3, sd1_data4, sd1_data5, sd1_data6, sd1_data7 1, 4, or 8-bit sd/mmc usdhc-2 gpio1_io04, g pio1_io08, gpio1_io07, sd2_reset_b, sd2_cd_b, sd2_wp, sd2_clk, sd2_cmd, sd2_data0, sd 2_data1, sd2_data2, sd2_data3 1 or 4-bit usb usb_otg phy
package information and contact assignments i.mx 8m dual / 8m quadlite / 8m quad applications processors da ta sheet for consumer pr oducts, rev. 0.1, 05/2018 nxp semiconductors 73 5 package information and contact assignments this section includes the cont act assignment information and me chanical package drawing. 5.1 17 x 17 mm package information 5.1.1 17 x 17 mm, 0.65 mm pitch, ball matrix figure 44 shows the top, bottom, and side vi ews of the 17 17 mm bga pack age.
i.mx 8m dual / 8m quadlite / 8m quad applications processors da ta sheet for consumer pr oducts, rev. 0.1, 05/2018 74 nxp semiconductors package information and contact assignments figure 44. 17 x 17 mm bga, package top, bottom, and side views
package information and contact assignments i.mx 8m dual / 8m quadlite / 8m quad applications processors da ta sheet for consumer pr oducts, rev. 0.1, 05/2018 nxp semiconductors 75 5.1.2 17 x 17 mm supplies contact as signments and functional conta ct assignments table 82 shows supplies contact assignm ents for the 17 x 17 mm package. table 82. i.mx 8m dual / 8m quadlite / 8m quad 17 x 17 mm supplies contact assignments supply rail name ball( s) postion(s) remark efuse_vqps r17 supply for efuse programming hdmi_avddclk v3 supply for hdmi phy hdmi_avddcore u3, u4 supply for hdmi phy hdmi_avddio p2 supply for hdmi phy mipi_vdd e15, f15 supply for mipi phy mipi_vdda e17, e18, f17, f 18 supply for mipi phy mipi_vddha c18, d17, d18 supply for mipi phy mipi_vddpll f19 supply for mipi phy nvcc_daram y12, y14, aa10, aa15, ab3, ab8, ab17, ab23, ac3, ac6, ac8, ac14, ac17, ac20, ac23, ad5, ad18, ad21 supply for dram interface nvcc_ecspi f5 supply for escpi interface nvcc_enet t18 supply for enet interface nvcc_gpio1 r5, r6 supply for gpio1 interface nvcc_i2c h7 supply for i2c interface nvcc_jtag w4 supply for jtag interface nvcc_nand l18, m18 suppl y for nand interface nvcc_sai1 k3, l3 supply for sai interface nvcc_sai2 j7 supply for sai interface nvcc_sai3 e3 supply for sai interface nvcc_sai5 m3 supply for sai interface nvcc_sd1 l23, m23 suppl y for sd interface nvcc_sd2 n23 supply for sd interface nvcc_snvs w18 supply fo r snvs interface nvcc_uart d8 supply for uart interface pcie_vp f22, g22 supply for pcie phy pcie_vph h23, j23 supply for pcie phy pcie_vptx f23, g23 supply for pcie phy usb1_dvdd e12 supply for usb phy usb1_vdd33 g12 supply for usb phy usb1_vp d12 supply for usb phy
i.mx 8m dual / 8m quadlite / 8m quad applications processors da ta sheet for consumer pr oducts, rev. 0.1, 05/2018 76 nxp semiconductors package information and contact assignments usb1_vph f12 supply for usb phy usb1_vptx c12 supply for usb phy usb2_dvdd e11 supply for usb phy usb2_vdd33 g11 supply for usb phy usb2_vp d11 supply for usb phy usb2_vph f11 supply for usb phy usb2_vptx c11 supply for usb phy vdd_arm g14, g15, g16, h14, h15, h16, j15, j16, k15, k16, l15, l16, m15, m16 supply for arm core vdd_dram u10, u11, u12, u13 , u14, v9, v10, v11, v12, v13, v14, v15, y6, y8, y10, y16, y18, y20 supply for dram module vdd_gpu j9, j10, k9, k10, l9, l10, m9, m10 supply for gpu vdd_snvs r18 supply for snvs logic vdd_soc k12, l12, l13, m12, m 13, n13, p12, p13, p15, p16, r8, r9, r10, r11, r12 , r13, r14, r15, r16, t8, t17 supply for soc logic vdd_vpu n8, n9, n10, p 9, p10 supply for vpu vdda_0p9 v18 supply for soc logic vdda_1p8_fpll u17 supply for frac pll vdda_1p8_fpll_arm k14 supply for arm pll vdda_1p8_lvds u23 supply for lvds interface vdda_1p8_spll w17 supply for sscg pll vdda_1p8_spll_dram t15 supply for dram pll vdda_1p8_spll_video2 n11 supply for video pll2 vdda_1p8_tsensor t16 supply for temperature sensor vdda_1p8_xtal_25m w24 supply for xtal vdda_1p8_xtal_27m w23 supply for xtal vdda_dram aa11 supply for dram module table 82. i.mx 8m dual / 8m quadl ite / 8m quad 17 x 17 mm supplies contact assignments (continued)
package information and contact assignments i.mx 8m dual / 8m quadlite / 8m quad applications processors da ta sheet for consumer pr oducts, rev. 0.1, 05/2018 nxp semiconductors 77 table 83 shows an alpha-sorted list of f unctional contact assignments f or the 17 x 17 mm package. vss a2, a24, b1, b25, c8, c10, c13, c15, c24, d10, d13, d15, d23, e4, e10, e 13, e14, e16, e19, e20, e21, e22, e23, f10, f13, f14, f16, f20, g9, g10, g13, g17, g18, g24, h8, h9, h10, h11, h12, h13, h17, h18, j3, j8, j11, j 12, j13, j14, j17, j18, j19, k8, k11, k17, k18, k23, l 8, l11, l14, l17, m8, m11, m14, m17, n3, n14 , n15, n16, n17, n18, p6, p8, p11, p14, p17, p18, p23, r7, t3, t4, t9, t10, t11, t12, t13, u8, u9, u15, u18, v4, v8, v16, w1, w7, w8, w9, w10, w11, w12, w13, w14, w15, w16, w 25, y2, y3, y4, y5, y7, y9, y11, y13, y15, y17, y 19, y21, y22, y23, y24, aa5, aa16, aa21, ab2, ab9, ab11, ab18, ab24, ac4, ac19, ac22, ad1, ad7, ad9, ad11, ad13, ad16, ad 25, ae2, ae5, ae21, ae24 vssa_fpll u16 return path of vdda_1p8_fpll vssa_fpll_arm k13 return path of vdda_1p8_fpll_arm vssa_spll v17 return path of vdda_1p8_spll vssa_spll_dram t14 return path of vdda_1p8_spll_dram vssa_spll_video2 n12 return path of vdda_1p8_spll_video2 vssa_xtal_25m v23 return path of vdda_1p8_xtal_25m vssa_xtal_27m w22 return path of vdda_1p8_xtal_27m table 83. i.mx 8m dual / 8m quadl ite / 8m quad 17 x 17 mm function al contact assignments ball name ball power group ball type 1 reset condition 2 default mode (reset mode) default function (signal name) input/ output value boot_mode0 w6 nvcc_jtag gpio alt0 ccmsrcgpcmix.boot_mo de[0] input pd (90 k) boot_mode1 v6 nvcc_jtag gpio alt0 ccmsrcgpcmix.boot_mo de[1] input pd (90 k) clk1_p r23 vdda lvds clk1_n t23 vdda lvds clk2_p t22 vdda lvds clk2_n u22 vdda lvds dram_ac00 ac16 nvcc_dram ddr dram_ac01 ae17 nvcc_dram ddr table 82. i.mx 8m dual / 8m quadl ite / 8m quad 17 x 17 mm supplies contact assignments (continued)
i.mx 8m dual / 8m quadlite / 8m quad applications processors da ta sheet for consumer pr oducts, rev. 0.1, 05/2018 78 nxp semiconductors package information and contact assignments dram_ac02 ae18 nvcc_dram ddr dram_ac03 ac18 nvcc_dram ddr dram_ac04 ad14 nvcc_dram ddr dram_ac05 ae14 nvcc_dram ddr dram_ac06 ae13 nvcc_dram ddr dram_ac07 ab15 nvcc_dram ddr dram_ac08 ad17 nvcc_dram ddr dram_ac09 ae16 nvcc_dram ddr dram_ac10 ad20 nvcc_dram ddr dram_ac11 ae20 nvcc_dram ddr dram_ac12 ad19 nvcc_dram ddr dram_ac13 ae19 nvcc_dram ddr dram_ac14 ab16 nvcc_dram ddr dram_ac15 ac15 nvcc_dram ddr dram_ac16 ae15 nvcc_dram ddr dram_ac17 ad15 nvcc_dram ddr dram_ac19 ab14 nvcc_dram ddr dram_ac20 ad10 nvcc_dram ddr dram_ac21 ae10 nvcc_dram ddr dram_ac22 ad8 nvcc_dram ddr dram_ac23 ac9 nvcc_dram ddr dram_ac24 ad12 nvcc_dram ddr dram_ac25 ae12 nvcc_dram ddr dram_ac26 ab12 nvcc_dram ddr dram_ac27 aa12 nvcc_dram ddr dram_ac28 ac7 nvcc_dram ddr dram_ac29 ae7 nvcc_dram ddr dram_ac30 ae6 nvcc_dram ddr dram_ac31 ad6 nvcc_dram ddr dram_ac32 ae8 nvcc_dram ddr table 83. i.mx 8m dual / 8m quadlite / 8m quad 17 x 17 mm function al contact assignments (continued) ball name ball power group ball type 1 reset condition 2 default mode (reset mode) default function (signal name) input/ output value
package information and contact assignments i.mx 8m dual / 8m quadlite / 8m quad applications processors da ta sheet for consumer pr oducts, rev. 0.1, 05/2018 nxp semiconductors 79 dram_ac33 ae9 nvcc_dram ddr dram_ac34 ac10 nvcc_dram ddr dram_ac35 ab10 nvcc_dram ddr dram_ac36 ac12 nvcc_dram ddr dram_ac37 ae11 nvcc_dram ddr dram_ac38 ac11 nvcc_dram ddr dram_alert_n ac13 nvcc_dram ddr dram_dm0 ad23 nvcc_dram ddr dram_dm1 ab20 nvcc_dram ddr dram_dm2 ad3 nvcc_dram ddr dram_dm3 ab6 nvcc_dram ddr dram_dq00 ae23 nvcc_dram ddr dram_dq01 ad24 nvcc_dram ddr dram_dq02 ae22 nvcc_dram ddr dram_dq03 ad22 nvcc_dram ddr dram_dq04 aa24 nvcc_dram ddr dram_dq05 y25 nvcc_dram ddr dram_dq06 aa25 nvcc_dram ddr dram_dq07 ab25 nvcc_dram ddr dram_dq08 ab22 nvcc_dram ddr dram_dq09 aa22 nvcc_dram ddr dram_dq10 aa23 nvcc_dram ddr dram_dq11 aa20 nvcc_dram ddr dram_dq12 aa18 nvcc_dram ddr dram_dq13 ab19 nvcc_dram ddr dram_dq14 aa19 nvcc_dram ddr dram_dq15 aa17 nvcc_dram ddr dram_dq16 ae3 nvcc_dram ddr dram_dq17 ad2 nvcc_dram ddr dram_dq18 ae4 nvcc_dram ddr table 83. i.mx 8m dual / 8m quadlite / 8m quad 17 x 17 mm function al contact assignments (continued) ball name ball power group ball type 1 reset condition 2 default mode (reset mode) default function (signal name) input/ output value
i.mx 8m dual / 8m quadlite / 8m quad applications processors da ta sheet for consumer pr oducts, rev. 0.1, 05/2018 80 nxp semiconductors package information and contact assignments dram_dq19 ad4 nvcc_dram ddr dram_dq20 aa2 nvcc_dram ddr dram_dq21 y1 nvcc_dram ddr dram_dq22 aa1 nvcc_dram ddr dram_dq23 ab1 nvcc_dram ddr dram_dq24 ab4 nvcc_dram ddr dram_dq25 aa4 nvcc_dram ddr dram_dq26 aa3 nvcc_dram ddr dram_dq27 aa6 nvcc_dram ddr dram_dq28 aa8 nvcc_dram ddr dram_dq29 ab7 nvcc_dram ddr dram_dq30 aa7 nvcc_dram ddr dram_dq31 aa9 nvcc_dram ddr dram_dqs0_n ac25 nvcc_dram ddrclk dram_dqs0_p ac24 nvcc_dram ddrclk dram_dqs1_n ac21 nvcc_dram ddrclk dram_dqs1_p ab21 nvcc_dram ddrclk dram_dqs2_n ac1 nvcc_dram ddrclk dram_dqs2_p ac2 nvcc_dram ddrclk dram_dqs3_n ac5 nvcc_dram ddrclk dram_dqs3_p ab5 nvcc_dram ddrclk dram_reset_n ab13 nvcc_dram ddr dram_vref aa14 nvcc_dram ddr dram_zn aa13 nvcc_dram ddr ecspi1_miso b4 nvcc_ecspi gpio alt5 gpio5.io[8] input pd (90 k) ecspi1_mosi a4 nvcc_ecspi gpio alt5 gpio5.io[7] input pd (90 k) ecspi1_sclk d5 nvcc_ecspi gpio alt5 gpio5.io[6] input pd (90 k) ecspi1_ss0 d4 nvcc_ecspi gpio alt5 gpio5.io[9] input pd (90 k) ecspi2_miso b5 nvcc_ecspi gpio alt5 gpio5.io[12] input pd (90 k) ecspi2_mosi e5 nvcc_ecspi gpio alt5 gpio5.io[11] input pd (90 k) table 83. i.mx 8m dual / 8m quadlite / 8m quad 17 x 17 mm function al contact assignments (continued) ball name ball power group ball type 1 reset condition 2 default mode (reset mode) default function (signal name) input/ output value
package information and contact assignments i.mx 8m dual / 8m quadlite / 8m quad applications processors da ta sheet for consumer pr oducts, rev. 0.1, 05/2018 nxp semiconductors 81 ecspi2_sclk c5 nvcc_ecspi gpio alt5 gpio5.io[10] input pd (90 k) ecspi2_ss0 a5 nvcc_ecspi gpio alt5 gpio5.io[13] input pd (90 k) enet_mdc n20 nvcc_enet gpio alt5 gpio1.io[16] input pd (90 k) enet_mdio n19 nvcc_enet gpio alt5 gpio1.io[17] input pd (90 k) enet_rd0 u19 nvcc_enet gpio alt5 gpio1.io[26] input pd (90 k) enet_rd1 u21 nvcc_enet gpio alt5 gpio1.io[27] input pd (90 k) enet_rd2 u20 nvcc_enet gpio alt5 gpio1.io[28] input pd (90 k) enet_rd3 v19 nvcc_enet gpio alt5 gpio1.io[29] input pd (90 k) enet_rxc t20 nvcc_enet gpio alt5 gpio1.io[25] input pd (90 k) enet_rx_ctl t21 nvcc_enet gpio alt5 gpio1.io[24] input pd (90 k) enet_td0 r20 nvcc_enet gpio alt5 gpio1.io[21] input pd (90 k) enet_td1 r21 nvcc_enet gpio alt5 gpio1.io[20] input pd (90 k) enet_td2 r19 nvcc_enet gpio alt5 gpio1.io[19] input pd (90 k) enet_td3 p20 nvcc_enet gpio alt5 gpio1.io[18] input pd (90 k) enet_txc t19 nvcc_enet gpio alt5 gpio1.io[23] input pd (90 k) enet_tx_ctl p19 nvcc_enet gpio alt5 gpio1.io[22] input pd (90 k) gpio1_io00 t6 nvcc_gpio1 gpio alt0 gpio1.io[0] input pd (90 k) gpio1_io01 3 t7 nvcc_gpio1 gpio alt0 gpio1.io[1] input pd (90 k) gpio1_io02 r4 nvcc_gpio1 gpio alt0 gpio1.io[2] input pd (27 k) gpio1_io03 p4 nvcc_gpio1 gpio alt0 gpio1.io[3] input pd (90 k) gpio1_io04 p5 nvcc_gpio1 gpio alt0 gpio1.io[4] input pd (90 k) gpio1_io05 4 p7 nvcc_gpio1 gpio alt0 gpio1.io[5] input pu (27 k) gpio1_io06 n5 nvcc_gpio1 gpio alt0 gpio1.io[6] input pd (90 k) gpio1_io07 n6 nvcc_gpio1 gpio alt0 gpio1.io[7] input pd (90 k) gpio1_io08 n7 nvcc_gpio1 gpio alt0 gpio1.io[8] input pd (90 k) gpio1_io09 m6 nvcc_gpio1 gpio alt0 gpio1.io[9] input pd (90 k) gpio1_io10 m7 nvcc_gpio1 gpio alt0 gpio1.io[10] input pd (90 k) gpio1_io11 l6 nvcc_gpio1 gpio alt0 gpio1.io[11] input pd (90 k) gpio1_io12 l7 nvcc_gpio1 gpio alt0 gpio1.io[12] input pd (90 k) gpio1_io13 k6 nvcc_gpio1 gpio alt0 gpio1.io[13] input pd (90 k) table 83. i.mx 8m dual / 8m quadlite / 8m quad 17 x 17 mm function al contact assignments (continued) ball name ball power group ball type 1 reset condition 2 default mode (reset mode) default function (signal name) input/ output value
i.mx 8m dual / 8m quadlite / 8m quad applications processors da ta sheet for consumer pr oducts, rev. 0.1, 05/2018 82 nxp semiconductors package information and contact assignments gpio1_io14 k7 nvcc_gpio1 gpio alt0 gpio1.io[14] input pd (90 k) gpio1_io15 j6 nvcc_gpio1 gpio alt0 gpio1.io[15] input pd (90 k) hdmi_aux_n v2 hdmi_avddio phy hdmi_aux_p v1 hdmi_avddio phy hdmi_cec w3 hdmi_avddio phy hdmi_ddc_scl r3 hdmi_avddio phy hdmi_ddc_sda p3 hdmi_avddio phy hdmi_hpd w2 hdmi_avddio phy hdmi_refclk_n r1 hdmi_avddio phy hdmi_refclk_p r2 hdmi_avddio phy hdmi_rext p1 hdmi_avddio phy hdmi_tx_n_ln_0 t2 hdmi_avddio phy hdmi_tx_n_ln_1 u1 hdmi_avddio phy hdmi_tx_n_ln_2 n1 hdmi_avddio phy hdmi_tx_n_ln_3 m2 hdmi_avddio phy hdmi_tx_p_ln_0 t1 hdmi_avddio phy hdmi_tx_p_ln_1 u2 hdmi_avddio phy hdmi_tx_p_ln_2 n2 hdmi_avddio phy hdmi_tx_p_ln_3 m1 hdmi_avddio phy i2c1_scl e7 nvcc_i2c gpio alt5 gpio5.io[14] input pd (90 k) i2c1_sda e8 nvcc_i2c gpio alt5 gpio5.io[15] input pd (90 k) i2c2_scl g7 nvcc_i2c gpio alt5 gpio5.io[16] input pd (90 k) i2c2_sda f7 nvcc_i2c gpio alt5 gpio5.io[17] input pd (90 k) i2c3_scl g8 nvcc_i2c gpio alt5 gpio5.io[18] input pd (90 k) i2c3_sda e9 nvcc_i2c gpio alt5 gpio5.io[19] input pd (90 k) i2c4_scl f8 nvcc_i2c gpio alt5 gpio5.io[20] input pd (90 k) i2c4_sda f9 nvcc_i2c gpio alt5 gpio5.io[21] input pd (90 k) jtag_mod u7 nvcc_jtag gpio alt0 cjtag_wrapper.mod input pd (90 k) jtag_tck t5 nvcc_jtag gpio alt0 cjtag_wrapper.tck input pu 27 k) jtag_tdi w5 nvcc_jtag gpio alt0 cjtag_wrapper.tdi input pu (27 k) table 83. i.mx 8m dual / 8m quadlite / 8m quad 17 x 17 mm function al contact assignments (continued) ball name ball power group ball type 1 reset condition 2 default mode (reset mode) default function (signal name) input/ output value
package information and contact assignments i.mx 8m dual / 8m quadlite / 8m quad applications processors da ta sheet for consumer pr oducts, rev. 0.1, 05/2018 nxp semiconductors 83 jtag_tdo u5 nvcc_jtag gpio alt0 cjtag_wrapper.tdo input pu (27 k) jtag_tms v5 nvcc_jtag gpio alt0 cjtag_wrapper.tms input pu (27 k) jtag_trst_b u6 nvcc_jtag gpio alt0 cjtag_wrapper.trst_b input pu (27 k) mipi_csi1_clk_n a22 mipi_vddha phy mipi_csi1_clk_p b22 mipi_vddha phy mipi_csi1_d0_n a23 mipi_vddha phy mipi_csi1_d0_p b23 mipi_vddha phy mipi_csi1_d1_n c22 mipi_vddha phy mipi_csi1_d1_p d22 mipi_vddha phy mipi_csi1_d2_n b24 mipi_vddha phy mipi_csi1_d2_p c23 mipi_vddha phy mipi_csi1_d3_n c21 mipi_vddha phy mipi_csi1_d3_p d21 mipi_vddha phy mipi_csi2_clk_n a19 mipi_vddha phy mipi_csi2_clk_p b19 mipi_vddha phy mipi_csi2_d0_n c20 mipi_vddha phy mipi_csi2_d0_p d20 mipi_vddha phy mipi_csi2_d1_n a20 mipi_vddha phy mipi_csi2_d1_p b20 mipi_vddha phy mipi_csi2_d2_n a21 mipi_vddha phy mipi_csi2_d2_p b21 mipi_vddha phy mipi_csi2_d3_n c19 mipi_vddha phy mipi_csi2_d3_p d19 mipi_vddha phy mipi_dsi_clk_n c16 mipi_vddha phy mipi_dsi_clk_p d16 mipi_vddha phy mipi_dsi_d0_n a17 mipi_vddha phy mipi_dsi_d0_p b17 mipi_vddha phy mipi_dsi_d1_n a16 mipi_vddha phy mipi_dsi_d1_p b16 mipi_vddha phy mipi_dsi_d2_n a18 mipi_vddha phy table 83. i.mx 8m dual / 8m quadlite / 8m quad 17 x 17 mm function al contact assignments (continued) ball name ball power group ball type 1 reset condition 2 default mode (reset mode) default function (signal name) input/ output value
i.mx 8m dual / 8m quadlite / 8m quad applications processors da ta sheet for consumer pr oducts, rev. 0.1, 05/2018 84 nxp semiconductors package information and contact assignments mipi_dsi_d2_p b18 mipi_vddha phy mipi_dsi_d3_n a15 mipi_vddha phy mipi_dsi_d3_p b15 mipi_vddha phy mipi_dsi_rext c17 mipi_vddha phy nand_ale g19 nvcc_nand gpio alt5 gpio3.io[0] input pd (90 k) nand_ce0_b h19 nvcc_nand gpio alt5 gpio3.io[1] input pd (90 k) nand_ce1_b g21 nvcc_nand gpio alt5 gpio3.io[2] input pd (90 k) nand_ce2_b f21 nvcc_nand gpio alt5 gpio3.io[3] input pd (90 k) nand_ce3_b h20 nvcc_nand gpio alt5 gpio3.io[4] input pd (90 k) nand_cle h21 nvcc_nand gpio alt5 gpio3.io[5] input pd (90 k) nand_data00 g20 nvcc_nand gpio alt5 gpio3.io[6] input pd (90 k) nand_data01 j20 nvcc_nand gpio alt5 gpio3.io[7] input pd (90 k) nand_data02 h22 nvcc_nand gpio alt5 gpio3.io[8] input pd (90 k) nand_data03 j21 nvcc_nand gpio alt5 gpio3.io[9] input pd (90 k) nand_data04 l20 nvcc_nand gpio alt5 gpio3.io[10] input pd (90 k) nand_data05 j22 nvcc_nand gpio alt5 gpio3.io[11] input pd (90 k) nand_data06 l19 nvcc_nand gpio alt5 gpio3.io[12] input pd (90 k) nand_data07 m19 nvcc_nand gpio alt5 gpio3.io[13] input pd (90 k) nand_dqs m20 nvcc_nand gpio alt5 gpio3.io[14] input pd (90 k) nand_re_b k19 nvcc_nand gpio alt5 gpio3.io[15] input pd (90 k) nand_ready_b k20 nvcc_nand gpio alt5 gpio3.io[16] input pd (90 k) nand_we_b k22 nvcc_nand gpio alt5 gpio3.io[17] input pd (90 k) nand_wp_b k21 nvcc_nand gpio alt5 gpio3.io[18] input pd (90 k) onoff w21 nvcc_snvs gpio alt0 snvsmix.onoff input pu (27 k) pcie1_ref_pad_c lk_n k24 pcie_vph phy pcie1_ref_pad_c lk_p k25 pcie_vph phy pcie1_resref g25 pcie_vph phy pcie1_rxn_n h24 pcie_vph phy table 83. i.mx 8m dual / 8m quadlite / 8m quad 17 x 17 mm function al contact assignments (continued) ball name ball power group ball type 1 reset condition 2 default mode (reset mode) default function (signal name) input/ output value
package information and contact assignments i.mx 8m dual / 8m quadlite / 8m quad applications processors da ta sheet for consumer pr oducts, rev. 0.1, 05/2018 nxp semiconductors 85 pcie1_rxn_p h25 pcie_vph phy pcie1_txn_n j24 pcie_vph phy pcie1_txn_p j25 pcie_vph phy pcie2_ref_pad_c lk_n f24 pcie_vph phy pcie2_ref_pad_c lk_p f25 pcie_vph phy pcie2_resref c25 pcie_vph phy pcie2_rxn_n d24 pcie_vph phy pcie2_rxn_p d25 pcie_vph phy pcie2_txn_n e24 pcie_vph phy pcie2_txn_p e25 pcie_vph phy pmic_on_req v20 nvcc_snvs gpio alt0 snvsmix.pmic_on_req output open-drain pu (27 k) pmic_stby_req v21 nvcc_snvs gpio alt0 ccmsrcgpcmix.pmic_stb y_req output low por_b w20 nvcc_snvs gpio alt0 snvsmix.por_b input pu (27 k) rtc v22 nvcc_snvs gpio alt0 snvsmix.rtc input pd (90 k) rtc_reset_b w19 nvcc_snvs gpio alt0 snvsmix.rtc_por_b input pu (27 k) sai1_mclk a3 nvcc_sai1 gpio alt5 gpio4.io[20] input pd (90 k) sai1_rxc k1 nvcc_sai1 gpio alt5 gpio4.io[1] input pd (90 k) sai1_rxd0 5 k2 nvcc_sai1 gpio alt5 gpio4.io[2] input pd (90 k) sai1_rxd1 5 l2 nvcc_sai1 gpio alt5 gpio4.io[3] input pd (90 k) sai1_rxd2 5 h2 nvcc_sai1 gpio alt5 gpio4.io[4] input pd (90 k) sai1_rxd3 5 j2 nvcc_sai1 gpio alt5 gpio4.io[5] input pd (90 k) sai1_rxd4 5 j1 nvcc_sai1 gpio alt5 gpio4.io[6] input pd (90 k) sai1_rxd5 5 f1 nvcc_sai1 gpio alt5 gpio4.io[7] input pd (90 k) sai1_rxd6 5 g2 nvcc_sai1 gpio alt5 gpio4.io[8] input pd (90 k) sai1_rxd7 5 g1 nvcc_sai1 gpio alt5 gpio4.io[9] input pd (90 k) sai1_rxfs l1 nvcc_sai1 gpio alt5 gpio4.io[0] input pd (90 k) sai1_txc e1 nvcc_sai1 gpio alt5 gpio4.io[11] input pd (90 k) table 83. i.mx 8m dual / 8m quadlite / 8m quad 17 x 17 mm function al contact assignments (continued) ball name ball power group ball type 1 reset condition 2 default mode (reset mode) default function (signal name) input/ output value
i.mx 8m dual / 8m quadlite / 8m quad applications processors da ta sheet for consumer pr oducts, rev. 0.1, 05/2018 86 nxp semiconductors package information and contact assignments sai1_txd0 5 f2 nvcc_sai1 gpio alt5 gpio4.io[12] input pd (90 k) sai1_txd1 5 e2 nvcc_sai1 gpio alt5 gpio4.io[13] input pd (90 k) sai1_txd2 5 b2 nvcc_sai1 gpio alt5 gpio4.io[14] input pd (90 k) sai1_txd3 5 d1 nvcc_sai1 gpio alt5 gpio4.io[15] input pd (90 k) sai1_txd4 5 d2 nvcc_sai1 gpio alt5 gpio4.io[16] input pd (90 k) sai1_txd5 5 c2 nvcc_sai1 gpio alt5 gpio4.io[17] input pd (90 k) sai1_txd6 5 b3 nvcc_sai1 gpio alt5 gpio4.io[18] input pd (90 k) sai1_txd7 5 c1 nvcc_sai1 gpio alt5 gpio4.io[19] input pd (90 k) sai1_txfs h1 nvcc_sai1 gpio alt5 gpio4.io[10] input pd (90 k) sai2_mclk h5 nvcc_sai2 gpio alt5 gpio4.io[27] input pd (90 k) sai2_rxc h3 nvcc_sai2 gpio alt5 gpio4.io[22] input pd (90 k) sai2_rxd0 h6 nvcc_sai2 gpio alt5 gpio4.io[23] input pd (90 k) sai2_rxfs j4 nvcc_sai2 gpio alt5 gpio4.io[21] input pd (90 k) sai2_txc j5 nvcc_sai2 gpio alt5 gpio4.io[25] input pd (90 k) sai2_txd0 g5 nvcc_sai2 gpio alt5 gpio4.io[26] input pd (90 k) sai2_txfs h4 nvcc_sai2 gpio alt5 gpio4.io[24] input pd (90 k) sai3_mclk d3 nvcc_sai3 gpio alt5 gpio5.io[2] input pd (90 k) sai3_rxc f4 nvcc_sai3 gpio alt5 gpio4.io[29] input pd (90 k) sai3_rxd f3 nvcc_sai3 gpio alt5 gpio4.io[30] input pd (90 k) sai3_rxfs g4 nvcc_sai3 gpio alt5 gpio4.io[28] input pd (90 k) sai3_txc c4 nvcc_sai3 gpio alt5 gpio5.io[0] input pd (90 k) sai3_txd c3 nvcc_sai3 gpio alt5 gpio5.io[1] input pd (90 k) sai3_txfs g3 nvcc_sai3 gpio alt5 gpio4.io[31] input pd (90 k) sai5_mclk k4 nvcc_sai5 gpio alt5 gpio3.io[25] input pd (90 k) sai5_rxc l5 nvcc_sai5 gpio alt5 gpio3.io[20] input pd (90 k) sai5_rxd0 m5 nvcc_sai5 gpio alt5 gpio3.io[21] input pd (90 k) sai5_rxd1 l4 nvcc_sai5 gpio alt5 gpio3.io[22] input pd (90 k) sai5_rxd2 m4 nvcc_sai5 gpio alt5 gpio3.io[23] input pd (90 k) sai5_rxd3 k5 nvcc_sai5 gpio alt5 gpio3.io[24] input pd (90 k) sai5_rxfs n4 nvcc_sai5 gpio alt5 gpio3.io[19] input pd (90 k) table 83. i.mx 8m dual / 8m quadlite / 8m quad 17 x 17 mm function al contact assignments (continued) ball name ball power group ball type 1 reset condition 2 default mode (reset mode) default function (signal name) input/ output value
package information and contact assignments i.mx 8m dual / 8m quadlite / 8m quad applications processors da ta sheet for consumer pr oducts, rev. 0.1, 05/2018 nxp semiconductors 87 sd1_clk l25 nvcc_sd1 gpio alt5 gpio2.io[0] input pd (90 k) sd1_cmd l24 nvcc_sd1 gpio alt5 gpio2.io[1] input pd (90 k) sd1_data0 m25 nvcc_sd1 gpio alt5 gpio2.io[2] input pd (90 k) sd1_data1 m24 nvcc_sd1 gpio alt5 gpio2.io[3] input pd (90 k) sd1_data2 n25 nvcc_sd1 gpio alt5 gpio2.io[4] input pd (90 k) sd1_data3 p25 nvcc_sd1 gpio alt5 gpio2.io[5] input pd (90 k) sd1_data4 n24 nvcc_sd1 gpio alt5 gpio2.io[6] input pd (90 k) sd1_data5 p24 nvcc_sd1 gpio alt5 gpio2.io[7] input pd (90 k) sd1_data6 r25 nvcc_sd1 gpio alt5 gpio2.io[8] input pd (90 k) sd1_data7 t25 nvcc_sd1 gpio alt5 gpio2.io[9] input pd (90 k) sd1_reset_b r24 nvcc_sd1 gpio alt5 gpio2.io[10] input pd (90 k) sd1_strobe t24 nvcc_sd1 gpio alt5 gpio2.io[11] input pd (90 k) sd2_cd_b l21 nvcc_sd2 gpio alt5 gpio2.io[12] input pd (90 k) sd2_clk l22 nvcc_sd2 gpio alt5 gpio2.io[13] input pd (90 k) sd2_cmd m22 nvcc_sd2 gpio alt5 gpio2.io[14] input pd (90 k) sd2_data0 n22 nvcc_sd2 gpio alt5 gpio2.io[15] input pd (90 k) sd2_data1 n21 nvcc_sd2 gpio alt5 gpio2.io[16] input pd (90 k) sd2_data2 p22 nvcc_sd2 gpio alt5 gpio2.io[17] input pd (90 k) sd2_data3 p21 nvcc_sd2 gpio alt5 gpio2.io[18] input pd (90 k) sd2_reset_b r22 nvcc_sd2 gpio alt5 gpio2.io[19] input pd (90 k) sd2_wp m21 nvcc_sd2 gpio alt5 gpio2.io[20] input pd (90 k) spdif_ext_clk e6 nvcc_sai3 gpio alt5 gpio5.io[5] input pd (90 k) spdif_rx g6 nvcc_sai3 gpio alt5 gpio5.io[4] input pd (90 k) spdif_tx f6 nvcc_sai3 gpio alt5 gpio5.io[3] input pd (90 k) test_mode v7 nvcc_jtag gpio alt0 tcu.test_mode input pd (90 k) uart1_rxd c7 nvcc_uart gpio alt5 gpio5.io[22] input pd (90 k) uart1_txd a7 nvcc_uart gpio alt5 gpio5.io[23] input pd (90 k) uart2_rxd b6 nvcc_uart gpio alt5 gpio5.io[24] input pd (90 k) uart2_txd d6 nvcc_uart gpio alt5 gpio5.io[25] input pd (90 k) uart3_rxd a6 nvcc_uart gpio alt5 gpio5.io[26] input pd (90 k) table 83. i.mx 8m dual / 8m quadlite / 8m quad 17 x 17 mm function al contact assignments (continued) ball name ball power group ball type 1 reset condition 2 default mode (reset mode) default function (signal name) input/ output value
i.mx 8m dual / 8m quadlite / 8m quad applications processors da ta sheet for consumer pr oducts, rev. 0.1, 05/2018 88 nxp semiconductors package information and contact assignments uart3_txd b7 nvcc_uart gpio alt5 gpio5.io[27] input pd (90 k) uart4_rxd c6 nvcc_uart gpio alt5 gpio5.io[28] input pd (90 k) uart4_txd d7 nvcc_uart gpio alt5 gpio5.io[29] input pd (90 k) usb1_dn b14 usb1_vdd33 phy usb1_dp a14 usb1_vdd33 phy usb1_id c14 usb1_vdd33 phy usb1_resref a11 usb1_vph phy usb1_rx_n b12 usb1_vph phy usb1_rx_p a12 usb1_vph phy usb1_tx_n b13 usb1_vph phy usb1_tx_p a13 usb1_vph phy usb1_vbus d14 usb1_vdd33 phy usb2_dn b10 usb2_vdd33 phy usb2_dp a10 usb2_vdd33 phy usb2_id c9 usb2_vdd33 phy usb2_resref b11 usb2_vph phy usb2_rx_n b8 usb2_vph phy usb2_rx_p a8 usb2_vph phy usb2_tx_n b9 usb2_vph phy usb2_tx_p a9 usb2_vph phy usb2_vbus d9 usb2_vdd33 phy xtali_25m u25 vdda analog xtali_27m v25 vdda analog xtalo_25m u24 vdda analog xtalo_27m v24 vdda analog 1 the state immediately after reset and before rom firmware or so ftware has executed. 2 the state during, after reset and before rom firmware or softwa re has executed. 3 jtag active output during reset 4 int_boot output (high) during reset 5 boot configure input table 83. i.mx 8m dual / 8m quadlite / 8m quad 17 x 17 mm function al contact assignments (continued) ball name ball power group ball type 1 reset condition 2 default mode (reset mode) default function (signal name) input/ output value
package information and contact assignments i.mx 8m dual / 8m quadlite / 8m quad applications processors da ta sheet for consumer pr oducts, rev. 0.1, 05/2018 nxp semiconductors 89 5.1.3 i.mx 8m dual / 8m quadlite / 8m quad 17 x 17 mm 0.65 mm pitch ball map table 84 shows the i.mx 8m dual / 8m quadlite / 8m quad 17 x 17 mm, 0.65 mm pitch ball map. table 84. 17 x 17 mm, 0.65 mm pitch ball map 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 a vss sai1_mclk ecspi1_mosi ecspi2_ss0 uart3_rxd uart1_txd usb2_rx_p usb2_tx_p usb2_dp usb1_resref usb1_rx_p usb1_tx_p usb1_dp mipi_dsi_d3_n mipi_dsi_d1_n mipi_dsi_d0_n mipi_dsi_d2_n mipi_csi2_clk_n mipi_csi2_d1_n mipi_csi2_d2_n mipi_cs1_clk_n mipi_csi1_d0_n vss b vss sai1_txd2 sai1_txd6 ecspi1_miso ecspi2_miso uart2_rxd uart3_txd usb2_rx_n usb2_tx_n usb2_dn usb2_resref usb1_rx_n usb1_tx_n usb1_dn mipi_dsi_d3_p mipi_dsi_d1_p mipi_dsi_d0_p mipi_dsi_d2_p mipi_csi2_clk_p mipi_csi2_d1_p mipi_csi2_d2_p mipi_csi1_clk_p mipi_csi1_d0_p mipi_csi1_d2_n vss c sai1_txd7 sai1_txd5 sai3_txd sai3_txc ecspi2_sclk uart4_rxd uart1_rxd vss usb2_id vss usb2_vptx usb1_vptx vss usb1_id vss mipi_dsi_clk_n mipi_dsi_rext mipi_vddha mipi_csi2_d3_n mipi_csi2_d0_n mipi_csi1_d3_n mipi_csi1_d1_n mipi_csi1_d2_p vss pcie2_resref d sai1_txd3 sai1_txd4 sai3_mclk ecspi1_ss0 ecspi1_sclk uart2_txd uart4_txd nvcc_uart usb2_vbus vss usb2_vp usb1_vp vss usb1_vbus vss mipi_dsi_clk_p mipi_vddha mipi_vddha mipi_csi2_d3_p mipi_csi2_d0_p mipi_csi1_d3_p mipi_csi1_d1_p vss pcie2_rxn_n pcie2_rxn_p e sai1_txc sai1_txd1 nvcc_sai3 vss ecspi2_mosi spdif_ext_clk i2c1_scl i2c1_sda i2c3_sda vss usb2_dvdd usb1_dvdd vss vss mipi_vdd vss mipi_vdda mipi_vdda vss vss vss vss vss pcie2_txn_n pcie2_txn_p f sai1_rxd5 sai1_txd0 sai3_rxd sai3_rxc nvcc_ecspi spdif_tx i2c2_sda i2c4_scl i2c4_sda vss usb2_vph usb1_vph vss vss mipi_vdd vss mipi_vdda mipi_vdda mipi_vddpll vss nand_ce2_b pcie_vp pcie_vptx pcie2_ref_pad_clk_n pcie2_ref_pad_clk_p
i.mx 8m dual / 8m quadlite / 8m quad applications processors da ta sheet for consumer pr oducts, rev. 0.1, 05/2018 90 nxp semiconductors package information and contact assignments g sai1_rxd7 sai1_rxd6 sai3_txfs sai3_rxfs sai2_txd0 spdif_rx i2c2_scl i2c3_scl vss vss usb2_vdd33 usb1_vdd33 vss vdd_arm vdd_arm vdd_arm vss vss nand_ale nand_data00 nand_ce1_b pcie_vp pcie_vptx vss pcie1_resref h sai1_txfs sai1_rxd2 sai2_rxc sai2_txfs sai2_mclk sai2_rxd0 nvcc_i2c vss vss vss vss vss vss vdd_arm vdd_arm vdd_arm vss vss nand_ce0_b nand_ce3_b nand_cle nand_data02 pcie_vph pcie1_rxn_n pcie1_rxn_p j sai1_rxd4 sai1_rxd3 vss sai2_rxfs sai2_txc gpio1_io15 nvcc_sai2 vss vdd_gpu vdd_gpu vss vss vss vss vdd_arm vdd_arm vss vss vss nand_data01 nand_data03 nand_data05 pcie_vph pcie1_txn_n pcie1_txn_p k sai1_rxc sai1_rxd0 nvcc_sai1 sai5_mclk sai5_rxd3 gpio1_io13 gpio1_io14 vss vdd_gpu vdd_gpu vss vdd_soc vssa_fpll_arm vdda_1p8_fpll-arm vdd_arm vdd_arm vss vss nand_re_b nand_ready_b nand_wp_b nand_we_b vss pcie1_ref_pad_clk_n pcie1_ref_pad_clk_p l sai1_rxfs sai1_rxd1 nvcc_sai1 sai5_rxd1 sai5_rxc gpio1_io11 gpio1_io12 vss vdd_gpu vdd_gpu vss vdd_soc vdd_soc vss vdd_arm vdd_arm vss nvcc_nand nand_data06 nand_data04 sd2_cd_b sd2_clk nvcc_sd1 sd1_cmd sd1_clk m hdmi_tx_p_ln_3 hdmi_tx_m_ln_3 nvcc_sai5 sai5_rxd2 sai5_rxd0 gpio1_io09 gpio1_io10 vss vdd_gpu vdd_gpu vss vdd_soc vdd_soc vss vdd_arm vdd_arm vss nvcc_nand nand_data07 nand_dqs sd2_wp sd2_cmd nvcc_sd1 sd1_data1 sd1_data0 n hdmi_tx_m_ln_2 hdmi_tx_p_ln_2 vss sai5_rxfs gpio1_io06 gpio1_io07 gpio1_io08 vdd_vpu vdd_vpu vdd_vpu vdda_1p8_spll_video2 vssa_spll_video2 vdd_soc vss vss vss vss vss enet_mdio enet_mdc sd2_data1 sd2_data0 nvcc_sd2 sd1_data4 sd1_data2 table 84. 17 x 17 mm, 0.65 mm pitch ball map (continued) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
package information and contact assignments i.mx 8m dual / 8m quadlite / 8m quad applications processors da ta sheet for consumer pr oducts, rev. 0.1, 05/2018 nxp semiconductors 91 p hdmi_rext hdmi_avddio hdmi_ddc_sda gpio1_io03 gpio1_io04 vss gpio1_io05 vss vdd_vpu vdd_vpu vss vdd_soc vdd_soc vss vdd_soc vdd_soc vss vss enet_tx_ctl enet_td3 sd2_data3 sd2_data2 vss sd1_data5 sd1_data3 r hdmi_refclk_n hdmi_refclk_p hdmi_ddc_scl gpio1_io02 nvcc_gpio1 nvcc_gpio1 vss vdd_soc vdd_soc vdd_soc vdd_soc vdd_soc vdd_soc vdd_soc vdd_soc vdd_soc efuse_vqps vdd_snvs enet_td2 enet_td0 enet_td1 sd2_reset_b clk1_p sd1_reset_b sd1_data6 t hdmi_tx_p_ln_0 hdmi_tx_m_ln_0 vss vss jtag_tck gpio1_io00 gpio1_io01 vdd_soc vss vss vss vss vss vssa_spll_dram vdda_1p8_spll_dram vdda_1p8_tsensor vdd_soc nvcc_enet enet_txc enet_rxc enet_rx_ctl clk2_p clk1_n sd1_strobe sd1_data7 u hdmi_tx_m_ln_1 hdmi_tx_p_ln_1 hdmi_avddcore hdmi_avddcore jtag_tdo jtag_trst_b jtag_mod vss vss vdd_dram vdd_dram vdd_dram vdd_dram vdd_dram vss vssa_fpll vdda_1p8_fpll vss enet_rd0 enet_rd2 enet_rd1 clk2_n vdda_1p8_lvds xtalo_25m xtali_25m v hdmi_aux_p hdmi_aux_n hdmi_avddclk vss jtag_tms boot_mode1 test_mode vss vdd_dram vdd_dram vdd_dram vdd_dram vdd_dram vdd_dram vdd_dram vss vssa_spll vdda_0p9 enet_rd3 pmic_on_req pmic_stby_req rtc vssa_xtal_25m xtalo_27m xtali_27m w vss hdmi_hpd hdmi_cec nvcc_jtag jtag_tdi boot_mode0 vss vss vss vss vss vss vss vss vss vss vdda_1p8_spll nvcc_snvs rtc_reset_b por_b onoff vssa_xtal_27m vdda_1p8_xtal_27m vdda_1p8_xtal_25m vss y dram_dq21 vss vss vss vss vdd_dram vss vdd_dram vss vdd_dram vss nvcc_dram vss nvcc_dram vss vdd_dram vss vdd_dram vss vdd_dram vss vss vss vss dram_dq05 table 84. 17 x 17 mm, 0.65 mm pitch ball map (continued) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
i.mx 8m dual / 8m quadlite / 8m quad applications processors da ta sheet for consumer pr oducts, rev. 0.1, 05/2018 92 nxp semiconductors package information and contact assignments 5.2 ddr pin function list for 17 x 17 mm package table 85 shows the ddr pin functio n list for 17 x 17 mm package. aa dram_dq22 dram_dq20 dram_dq26 dram_dq25 vss dram_dq27 dram_dq30 dram_dq28 dram_dq31 nvcc_dram vdda_dram dram_ac27 dram_zn dram_vref nvcc_dram vss dram_dq15 dram_dq12 dram_dq14 dram_dq11 vss dram_dq09 dram_dq10 dram_dq04 dram_dq06 ab dram_dq23 vss nvcc_dram dram_dq24 dram_dqs3_p dram_dm3 dram_dq29 nvcc_dram vss dram_ac35 vss dram_ac26 dram_reset_n dram_ac19 dram_ac07 dram_ac14 nvcc_dram vss dram_dq13 dram_dm1 dram_dqs1_p dram_dq08 nvcc_dram vss dram_dq07 ac dram_dqs2_n dram_dqs2_p nvcc_dram vss dram_dqs3_n nvcc_dram dram_ac28 nvcc_dram dram_ac23 dram_ac34 dram_ac38 dram_ac36 dram_alert_n nvcc_dram dram_ac15 dram_ac00 nvcc_dram dram_ac03 vss nvcc_dram dram_dqs1_n vss nvcc_dram dram_dqs0_p dram_dqs0_n ad vss dram_dq17 dram_dm2 dram_dq19 nvcc_dram dram_ac31 vss dram_ac22 vss dram_ac20 vss dram_ac24 vss dram_ac04 dram_ac17 vss dram_ac08 nvcc_dram dram_ac12 dram_ac10 nvcc_dram dram_dq03 dram_dm0 dram_dq01 vss ae vss dram_dq16 dram_dq18 vss dram_ac30 dram_ac29 dram_ac32 dram_ac33 dram_ac21 dram_ac37 dram_ac25 dram_ac06 dram_ac05 dram_ac16 dram_ac09 dram_ac01 dram_ac02 dram_ac13 dram_ac11 vss dram_dq02 dram_dq00 vss table 85. ddr pin function l ist for 17 x 17 mm package die level pin name lpddr4 ddr4 ddr3l ball dram_dqs0_p dqs0_t_a dqsl_t_a dqsl_a ac24 dram_dqs0_n dqs0_c_a dqsl_c_a dqsl#_a ac25 dram_dm0 dmi0_a dml_n_a / dbil_n_a dml_a ad23 dram_dq00 dq0_a dql0_a dql0_a ae23 dram_dq01 dq1_a dql1_a dql1_a ad24 dram_dq02 dq2_a dql2_a dql2_a ae22 dram_dq03 dq3_a dql3_a dql3_a ad22 dram_dq04 dq4_a dql4_a dql4_a aa24 dram_dq05 dq5_a dql5_a dql5_a y25 table 84. 17 x 17 mm, 0.65 mm pitch ball map (continued) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
package information and contact assignments i.mx 8m dual / 8m quadlite / 8m quad applications processors da ta sheet for consumer pr oducts, rev. 0.1, 05/2018 nxp semiconductors 93 dram_dq06 dq6_a dql6_a dql6_a aa25 dram_dq07 dq7_a dql7_a dql7_a ab25 dram_dqs1_p dqs1_t_a dqsu_t_a dqsu_a ab21 dram_dqs1_n dqs1_c_a dqsu_c_a dqsu#_a ac21 dram_dm1 dmi1_a dmu_n_a / dbiu_n_a dmu_a ab20 dram_dq08 dq08_a dqu0_a dqu0_a ab22 dram_dq09 dq09_a dqu1_a dqu1_a aa22 dram_dq10 dq10_a dqu2_a dqu2_a aa23 dram_dq11 dq11_a dqu3_a dqu3_a aa20 dram_dq12 dq12_a dqu4_a dqu4_a aa18 dram_dq13 dq13_a dqu5_a dqu5_a ab19 dram_dq14 dq14_a dqu6_a dqu6_a aa19 dram_dq15 dq15_a dqu7_a dqu7_a aa17 dram_dqs2_p dqs0_t_b dqsl_t_b dqsl_b ac2 dram_dqs2_n dqs0_c_b dqsl_c_b dqsl#_b ac1 dram_dm2 dmi0_b dml_n_b / dbil_n_b dml_b ad3 dram_dq16 dq0_b dql0_b dql0_b ae3 dram_dq17 dq1_b dql1_b dql1_b ad2 dram_dq18 dq2_b dql2_b dql2_b ae4 dram_dq19 dq3_b dql3_b dql3_b ad4 dram_dq20 dq4_b dql4_b dql4_b aa2 dram_dq20 dq4_b dql4_b dql4_b aa2 dram_dq21 dq5_b dql5_b dql5_b y1 dram_dq22 dq6_b dql6_b dql6_b aa1 dram_dq23 dq7_b dql7_b dql7_b ab1 dram_dqs3_p dqs1_t_b dqsu_t_b dqsu_b ab5 dram_dqs3_n dqs1_c_b dqsu_c_b dqsu#_b ac5 dram_dm3 dmi1_b dmu_n_b / dbiu_n_b dmu_b ab6 dram_dq24 dq08_b dqu0_b dqu0_b ab4 dram_dq25 dq09_b dqu1_b dqu1_b aa4 dram_dq26 dq10_b dqu2_b dqu2_b aa3 dram_dq27 dq11_b dqu3_b dqu3_b aa6 dram_dq28 dq12_b dqu4_b dqu4_b aa8 dram_dq29 dq13_b dqu5_b dqu5_b ab7 table 85. ddr pin function list fo r 17 x 17 mm package (continue d)
i.mx 8m dual / 8m quadlite / 8m quad applications processors da ta sheet for consumer pr oducts, rev. 0.1, 05/2018 94 nxp semiconductors package information and contact assignments dram_dq30 dq14_b dqu6_b dqu6_b aa7 dram_dq31 dq15_b dqu7_b dqu7_b aa9 dram_reset_n reset_n reset_n reset# ab13 dram_alert_n mtest1 alert_n / mtest1 mtest1 ac13 dram_ac00 cke0_a cke0 cke0 ac16 dram_ac01 cke1_a cke1 cke1 ae17 dram_ac02 cs0_a cs0_n cs0# ae18 dram_ac03 cs1_a c0 ac18 dram_ac04 ck_t_a bg0 ba2 ad14 dram_ac05 ck_c_a bg1 a14 ae14 dram_ac06 act_n a15 ae13 dram_ac07 a9 a9 ab15 dram_ac08 ca0_a a12 a12 / bc# ad17 dram_ac09 ca1_a a11 a11 ae16 dram_ac10 ca2_a a7 a7 ad20 dram_ac11 ca3_a a8 a8 ae20 dram_ac12 ca4_a a6 a6 ad19 dram_ac13 ca5_a a5 a5 ae19 dram_ac14 a4 a4 ab16 dram_ac15 a3 a3 ac15 dram_ac16 ck_t_a ck_a ae15 dram_ac17 ck_c_a ck#_a ad15 dram_ac19 mtest mtest mtest ab14 dram_ac20 cke0_b ck_t_b ck_b ad10 dram_ac21 cke1_b ck_c_b ck#_b ae10 dram_ac22 cs1_b ad8 dram_ac23 cs0_b ac9 dram_ac24 ck_t_b a2 a2 ad12 dram_ac25 ck_c_b a1 a1 ae12 dram_ac26 ba1 ba1 ab12 dram_ac27 parity aa12 dram_ac28 ca2_b a13 a13 ac7 dram_ac29 ca3_b ba0 ba0 ae7 dram_ac30 ca4_b a10 / ap a10 / ap ae6 table 85. ddr pin function list fo r 17 x 17 mm package (continue d)
package information and contact assignments i.mx 8m dual / 8m quadlite / 8m quad applications processors da ta sheet for consumer pr oducts, rev. 0.1, 05/2018 nxp semiconductors 95 dram_ac31 ca5_b a0 a0 ad6 dram_ac32 ca0_b c2 ae8 dram_ac33 ca1_b cas_n / a15 cas# ae9 dram_ac34 we_n / a14 we# ac10 dram_ac35 ras_n / a16 ras# ab10 dram_ac36 odt0 odt0 ac12 dram_ac37 odt1 odt1 ae11 dram_ac38 cs1_n cs1# ac11 dram_zn zq zq zq aa13 dram_vref vref vref vref aa14 table 85. ddr pin function list fo r 17 x 17 mm package (continue d)
i.mx 8m dual / 8m quadlite / 8m quad applications processors da ta sheet for consumer pr oducts, rev. 0.1, 05/2018 96 nxp semiconductors revision history 6 revision history table 86 provides a revision histor y for this data sheet. table 86. revision history rev. number date substantive change(s) rev. 0.1 05/2018 ? added a note in the table 2, "orderable part numbers" ? updated the table 3, "i.mx 8m dua l / 8m quadlite / 8m quad modules list" ? updated teh table 7, "operating ranges" ? updated the table 9, "maximum supply currents" ? updated the table 10, "chip power i n different lp mode" ? added the table 11, "the pow er supply states" ? updated the pcie parameters in the table 15, "pcie recomme nded operating conditions" ? updated and added a le akage limit note in the table 26, "gpio d c parameters" ? added a leakage limit note in the table 29, "input dc current" ? updated the timing parameters in the table 38, "ecspi master m ode timing parameters" and table 39, "ecspi slave mode timing parameters" ? updated the section 3.9.8.1, pci ex_resref reference resistor connection ? updated the table 58, "mipi input charact eristics dc specifications" ? removed the spi interfaces from the table 81, "interface allocation during boot" ? updated the pcie and mipi power group in the table 83, "i.mx 8m dual / 8m quadlite / 8m quad 17 x 17 mm functional contac t assignments" ? updated the table 84, "17 x 17 mm, 0. 65 mm pitch ball map" rev. 0 01/2018 ? initial version
document number: imx8mdqlqcec rev. 0.1 05/2018 information in this document is p rovided solely to enable syste m and software implementers to use nxp products. there are no e xpress or implied copyright lic enses granted hereunder to design or fabricate any integra ted circuits based on the inform ation in this document. nxp reserves the right to make changes without further notice to an y products herein. nxp makes no warranty, represen tation, or guarantee regarding t he suitability of its products for any particular purpose , nor does nxp assume any liability arisi ng out of the application or use of any product or circuit, and s pecifically disclaims any and a ll liability, including without limitation consequential or incid ental damages. typical param eters that may be provided in nxp data sheets and/or specifica tions can and do vary in differ ent applications, and actual performance may vary over time. a ll operating parameters, inclu ding typicals must be validated for each customer appl ication by customer? customers technical experts. nxp does not convey any license under its patent rights nor the rights o f others. nxp sells products pursuant to standard terms and conditions of sale, which can be found at the following address: nxp.com/salestermsandconditions. nxp, the nxp logo, freescale, the freescale logo, and the energ y efficient solutions logo are trademarks of nxp b.v. all other product or servi ce names are t he property of the ir respective owners. arm and cortex a re trademarks of arm limited (or its su bsidiaries) in the eu and/or elsewhere. all rights reserved. ? 2018 nxp b.v. how to reach us: home page: nxp.com web support: nxp.com/support

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